drivers: i3c: Move clocking code out of NXP I3C driver

The clocking code present inside the NXP I3C is SoC specific.
This has been moved to the SoC folder which makes this driver
more flexible to clock architecture variations between SoC's
and SDK driver clock API variations.

(cherry picked from commit f1b57f6)

Original-Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
GitOrigin-RevId: f1b57f6
Cr-Build-Id: 8735895478936220081
Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8735895478936220081
Copybot-Job-Name: zephyr-main-copybot-downstream
Change-Id: Ifd264bd7e5fdbbe6ea3f2aab7c63643411fc4097
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5887640
Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
Tested-by: Fabio Baltieri <fabiobaltieri@google.com>
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Commit-Queue: Fabio Baltieri <fabiobaltieri@google.com>

drivers/i3c/i3c_mcux.c

@@ -98,27 +98,8 @@ struct mcux_i3c_data {
 	/** Condvar for waiting for bus to be in IDLE state */
 	struct k_condvar condvar;
 
-	struct {
-		/**
-		 * Clock divider for use when generating clock for
-		 * I3C Push-pull mode.
-		 */
-		uint8_t clk_div_pp;
-
-		/**
-		 * Clock divider for use when generating clock for
-		 * I3C open drain mode.
-		 */
-		uint8_t clk_div_od;
-
-		/**
-		 * Clock divider for the slow time control clock.
-		 */
-		uint8_t clk_div_tc;
-
-		/** I3C open drain clock frequency in Hz. */
-		uint32_t i3c_od_scl_hz;
-	} clocks;
+	/** I3C open drain clock frequency in Hz. */
+	uint32_t i3c_od_scl_hz;
 
 #ifdef CONFIG_I3C_USE_IBI
 	struct {
@@ -1912,8 +1893,8 @@ static int mcux_i3c_configure(const struct device *dev,
 	master_config.baudRate_Hz.i3cPushPullBaud = ctrl_cfg->scl.i3c;
 	master_config.enableOpenDrainHigh = dev_cfg->disable_open_drain_high_pp ? false : true;
 
-	if (dev_data->clocks.i3c_od_scl_hz) {
-		master_config.baudRate_Hz.i3cOpenDrainBaud = dev_data->clocks.i3c_od_scl_hz;
+	if (dev_data->i3c_od_scl_hz) {
+		master_config.baudRate_Hz.i3cOpenDrainBaud = dev_data->i3c_od_scl_hz;
 	}
 
 	/* Initialize hardware */
@@ -1979,10 +1960,6 @@ static int mcux_i3c_init(const struct device *dev)
 		goto err_out;
 	}
 
-	CLOCK_SetClkDiv(kCLOCK_DivI3cClk, data->clocks.clk_div_pp);
-	CLOCK_SetClkDiv(kCLOCK_DivI3cSlowClk, data->clocks.clk_div_od);
-	CLOCK_SetClkDiv(kCLOCK_DivI3cTcClk, data->clocks.clk_div_tc);
-
 	ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
 	if (ret != 0) {
 		goto err_out;
@@ -2159,12 +2136,9 @@ static const struct i3c_driver_api mcux_i3c_driver_api = {
 			DT_INST_PROP(id, disable_open_drain_high_pp),		\
 	};									\
 	static struct mcux_i3c_data mcux_i3c_data_##id = {			\
-		.clocks.i3c_od_scl_hz = DT_INST_PROP_OR(id, i3c_od_scl_hz, 0),	\
+		.i3c_od_scl_hz = DT_INST_PROP_OR(id, i3c_od_scl_hz, 0),		\
 		.common.ctrl_config.scl.i3c = DT_INST_PROP_OR(id, i3c_scl_hz, 0),	\
 		.common.ctrl_config.scl.i2c = DT_INST_PROP_OR(id, i2c_scl_hz, 0),	\
-		.clocks.clk_div_pp = DT_INST_PROP(id, clk_divider),		\
-		.clocks.clk_div_od = DT_INST_PROP(id, clk_divider_slow),	\
-		.clocks.clk_div_tc = DT_INST_PROP(id, clk_divider_tc),		\
 	};									\
 	DEVICE_DT_INST_DEFINE(id,						\
 			      mcux_i3c_init,					\