soc: stm32g0: add fdcan2

The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.

(cherry picked from commit c1ae6e5)

Original-Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
GitOrigin-RevId: c1ae6e5
Change-Id: I3d1ec4c5a89d4d12698e9a6cdbd8e3bace2ff468
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5240562
Tested-by: Tristan Honscheid <honscheid@google.com>
Reviewed-by: Al Semjonovs <asemjonovs@google.com>
Reviewed-by: Tristan Honscheid <honscheid@google.com>
Tested-by: Al Semjonovs <asemjonovs@google.com>
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Commit-Queue: Al Semjonovs <asemjonovs@google.com>

dts/arm/st/g0/stm32g0b1.dtsi

@@ -43,6 +43,19 @@
 			status = "disabled";
 		};
 
+		fdcan2: can@40006800 {
+			compatible = "st,stm32-fdcan";
+			reg = <0x40006800 0x400>, <0x4000b750 0x350>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <21 0>, <22 0>;
+			interrupt-names = "int0", "int1";
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>;
+			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
+			sample-point = <875>;
+			sample-point-data = <875>;
+			status = "disabled";
+		};
+
 		usart5: serial@40005000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x40005000 0x400>;

soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx

@@ -11,4 +11,11 @@ config SOC
 config NUM_IRQS
 	default 31
 
+if CAN_STM32_FDCAN
+
+config SHARED_INTERRUPTS
+	default y if $(dt_nodelabel_enabled,fdcan1) && $(dt_nodelabel_enabled,fdcan2)
+
+endif # CAN_STM32_FDCAN
+
 endif # SOC_STM32G0B1XX