drivers: mipi_dsi: dsi_mcux_2l add property to enable non-continuous …

…hs clk

Allows device tree to enable usage of the controller feature
where HS clock is disabled when not in use, which is good
for reducing power consumption if MIPI DSI is mostly idle.

(cherry picked from commit 01aa800)

Original-Signed-off-by: Mike J. Chen <mjchen@google.com>
GitOrigin-RevId: 01aa800
Change-Id: I938be443feb10e81b3dd51c3b564613a6c51310c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/4971828
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Commit-Queue: Al Semjonovs <asemjonovs@google.com>
Tested-by: Al Semjonovs <asemjonovs@google.com>
Reviewed-by: Al Semjonovs <asemjonovs@google.com>

drivers/mipi_dsi/dsi_mcux_2l.c

@@ -28,6 +28,7 @@ struct mcux_mipi_dsi_config {
 	MIPI_DSI_HOST_Type *base;
 	dsi_dpi_config_t dpi_config;
 	bool auto_insert_eotp;
+	bool noncontinuous_hs_clk;
 	const struct device *bit_clk_dev;
 	clock_control_subsys_t bit_clk_subsys;
 	const struct device *esc_clk_dev;
@@ -224,6 +225,7 @@ static int dsi_mcux_attach(const struct device *dev,
 	DSI_GetDefaultConfig(&dsi_config);
 	dsi_config.numLanes = mdev->data_lanes;
 	dsi_config.autoInsertEoTp = config->auto_insert_eotp;
+	dsi_config.enableNonContinuousHsClk = config->noncontinuous_hs_clk;
 
 	/* Init the DSI module. */
 	DSI_Init(config->base, &dsi_config);
@@ -502,6 +504,7 @@ static int mcux_mipi_dsi_init(const struct device *dev)
 		(.irq_config_func = mipi_dsi_##n##_irq_config_func,))				\
 		.base = (MIPI_DSI_HOST_Type *)DT_INST_REG_ADDR(id),				\
 		.auto_insert_eotp = DT_INST_PROP(id, autoinsert_eotp),				\
+		.noncontinuous_hs_clk = DT_INST_PROP(id, noncontinuous_hs_clk),			\
 		.dphy_ref_freq = DT_INST_PROP_OR(id, dphy_ref_frequency, 0),			\
 		.bit_clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(id, dphy)),		\
 		.bit_clk_subsys =								\

dts/bindings/mipi-dsi/nxp,mipi-dsi-2l.yaml

@@ -70,3 +70,9 @@ properties:
     description:
       Maximum clock speed supported by the device, in Hz. Leave at default
       if no DPHY PLL is present
+
+  noncontinuous-hs-clk:
+    type: boolean
+    description:
+      Enable non-contiuous high speed clock. Saves power but introduces latency
+      when transitioning to high speed mode.