boards: ucans32k1sic: enable LPSPI support

Enable LPSPI support on ucans32k1sic board. (cherry picked from commit e4e3386) Original-Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com> GitOrigin-RevId: e4e3386 Change-Id: If4df58e69d62dade6de88f8173ca813020501348 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5099019 Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com> Commit-Queue: Fabio Baltieri <fabiobaltieri@google.com> Tested-by: Fabio Baltieri <fabiobaltieri@google.com> Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
coreboot · Dec 7, 2023 · 5ff59c6 · 5ff59c6
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diff --git a/boards/arm/ucans32k1sic/doc/index.rst b/boards/arm/ucans32k1sic/doc/index.rst
@@ -48,6 +48,7 @@ PORT          on-chip     pinctrl
 GPIO          on-chip     gpio
 LPUART        on-chip     serial
 LPI2C         on-chip     i2c
+LPSPI         on-chip     spi
 ============  ==========  ================================
 
 The default configuration can be found in the Kconfig file

diff --git a/boards/arm/ucans32k1sic/ucans32k1sic-pinctrl.dtsi b/boards/arm/ucans32k1sic/ucans32k1sic-pinctrl.dtsi
@@ -27,4 +27,14 @@
 			drive-strength = "low";
 		};
 	};
+
+	lpspi0_default: lpspi0_default {
+		group0 {
+			pinmux = <LPSPI0_SCK_PTB2>,
+				<LPSPI0_SIN_PTB3>,
+				<LPSPI0_SOUT_PTB4>,
+				<LPSPI0_PCS0_PTB5>;
+			drive-strength = "low";
+		};
+	};
 };
diff --git a/boards/arm/ucans32k1sic/ucans32k1sic.dts b/boards/arm/ucans32k1sic/ucans32k1sic.dts
@@ -98,3 +98,9 @@
 	sda-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
+
+&lpspi0 {
+	pinctrl-0 = <&lpspi0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/arm/ucans32k1sic/ucans32k1sic.yaml b/boards/arm/ucans32k1sic/ucans32k1sic.yaml
@@ -16,3 +16,4 @@ supported:
   - uart
   - pinctrl
   - i2c
+  - spi