boards: shields: rk055hdmipi4ma0: raise MIPI DSI bit clock for RT1170

The RT1170 MIPI DPHY requires a faster clock frequency setting for
the MIPI DPHY, or the pixel packet counts for the HFP, HBP, and HSA will
be incorrect, and the DSI transfers will stall. Raise the target DPHY
clock frequency to resolve this.

Fixes #78299

(cherry picked from commit 9c0f92d)

Original-Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
GitOrigin-RevId: 9c0f92d
Cr-Build-Id: 8735286451693989857
Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8735286451693989857
Copybot-Job-Name: zephyr-main-copybot-downstream
Change-Id: I2a264e56b49a4e94d570b0bcb99e4f1d7e7b93f5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5901773
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Tested-by: Al Semjonovs <asemjonovs@google.com>
Reviewed-by: Al Semjonovs <asemjonovs@google.com>
Commit-Queue: Al Semjonovs <asemjonovs@google.com>

boards/shields/rk055hdmipi4ma0/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay

@@ -0,0 +1,10 @@
+/*
+ * Copyright 2024, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&zephyr_mipi_dsi {
+	/* Raise the DSI clock frequency */
+	phy-clock = <792000000>;
+};