drivers: mdio_nxp_enet: Don't disable IRQ

No real need to be enabling and disabling IRQs, this logic has been
reported to be causing spurious interrupts and strange behavior, we can
just enable the interrupt and switch to interrupt based logic one time
and keep the interrupt enabled at that point.

Also, fix a W1C bug where |= was used instead of = to clear a flag.

(cherry picked from commit 2ab1046)

Original-Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
GitOrigin-RevId: 2ab1046
Cr-Build-Id: 8733565196572304993
Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8733565196572304993
Copybot-Job-Name: zephyr-main-copybot-downstream
Change-Id: Ibff2b9dd1b06bda968a9037a23c806d6f0dd45c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5934680
Tested-by: Dawid Niedźwiecki <dawidn@google.com>
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Commit-Queue: Dawid Niedźwiecki <dawidn@google.com>
Reviewed-by: Dawid Niedźwiecki <dawidn@google.com>

drivers/mdio/mdio_nxp_enet.c

@@ -41,17 +41,13 @@ struct nxp_enet_mdio_data {
 static int nxp_enet_mdio_wait_xfer(const struct device *dev)
 {
 	struct nxp_enet_mdio_data *data = dev->data;
-	ENET_Type *base = data->base;
 
 	/* This function will not make sense from IRQ context */
 	if (k_is_in_isr()) {
 		return -EWOULDBLOCK;
 	}
 
-	if (data->interrupt_up) {
-		/* Enable the interrupt */
-		base->EIMR |= ENET_EIMR_MII_MASK;
-	} else {
+	if (!data->interrupt_up) {
 		/* If the interrupt is not available to use yet, just busy wait */
 		k_busy_wait(CONFIG_MDIO_NXP_ENET_TIMEOUT);
 		k_sem_give(&data->mdio_sem);
@@ -77,7 +73,7 @@ static int nxp_enet_mdio_read(const struct device *dev,
 	 * Clear the bit (W1C) that indicates MDIO transfer is ready to
 	 * prepare to wait for it to be set once this read is done
 	 */
-	data->base->EIR |= ENET_EIR_MII_MASK;
+	data->base->EIR = ENET_EIR_MII_MASK;
 
 	/*
 	 * Write MDIO frame to MII management register which will
@@ -105,7 +101,7 @@ static int nxp_enet_mdio_read(const struct device *dev,
 	*read_data = (data->base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT;
 
 	/* Clear the same bit as before because the event has been handled */
-	data->base->EIR |= ENET_EIR_MII_MASK;
+	data->base->EIR = ENET_EIR_MII_MASK;
 
 	/* This MDIO interaction is finished */
 	(void)k_mutex_unlock(&data->mdio_mutex);
@@ -127,7 +123,7 @@ static int nxp_enet_mdio_write(const struct device *dev,
 	 * Clear the bit (W1C) that indicates MDIO transfer is ready to
 	 * prepare to wait for it to be set once this write is done
 	 */
-	data->base->EIR |= ENET_EIR_MII_MASK;
+	data->base->EIR = ENET_EIR_MII_MASK;
 
 	/*
 	 * Write MDIO frame to MII management register which will
@@ -153,7 +149,7 @@ static int nxp_enet_mdio_write(const struct device *dev,
 	}
 
 	/* Clear the same bit as before because the event has been handled */
-	data->base->EIR |= ENET_EIR_MII_MASK;
+	data->base->EIR = ENET_EIR_MII_MASK;
 
 	/* This MDIO interaction is finished */
 	(void)k_mutex_unlock(&data->mdio_mutex);
@@ -170,13 +166,9 @@ static void nxp_enet_mdio_isr_cb(const struct device *dev)
 {
 	struct nxp_enet_mdio_data *data = dev->data;
 
-	data->base->EIR |= ENET_EIR_MII_MASK;
+	data->base->EIR = ENET_EIR_MII_MASK;
 
-	/* Signal that operation finished */
 	k_sem_give(&data->mdio_sem);
-
-	/* Disable the interrupt */
-	data->base->EIMR &= ~ENET_EIMR_MII_MASK;
 }
 
 static void nxp_enet_mdio_post_module_reset_init(const struct device *dev)
@@ -212,7 +204,9 @@ void nxp_enet_mdio_callback(const struct device *dev,
 		nxp_enet_mdio_isr_cb(dev);
 		break;
 	case NXP_ENET_INTERRUPT_ENABLED:
+		/* IRQ was enabled in NVIC, now enable in enet */
 		data->interrupt_up = true;
+		data->base->EIMR |= ENET_EIMR_MII_MASK;
 		break;
 	default:
 		break;