soc: riscv: andes_v5: reorganize SoC folder

Split out from riscv-privileged folder, and create a new family. (cherry picked from commit 8027689) Original-Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> GitOrigin-RevId: 8027689 Change-Id: Ie26c768ccd94c3e1f156b53184ffadfab13f6416 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5180660 Commit-Queue: Tristan Honscheid <honscheid@google.com> Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com> Reviewed-by: Tristan Honscheid <honscheid@google.com> Tested-by: Tristan Honscheid <honscheid@google.com>
coreboot · Jan 10, 2024 · dd4d16d · dd4d16d
1 parent 4de2960
commit dd4d16d
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Showing 25 changed files with 55 additions and 26 deletions.
diff --git a/boards/riscv/adp_xc7k_ae350/Kconfig.board b/boards/riscv/adp_xc7k_ae350/Kconfig.board
@@ -3,4 +3,4 @@
 
 config BOARD_ADP_XC7K_AE350
 	bool "Andes ADP-XC7K AE350 Platform"
-	depends on SOC_RISCV_ANDES_AE350
+	depends on SOC_ANDES_AE350
diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig b/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig
@@ -1,5 +1,5 @@
-CONFIG_SOC_SERIES_RISCV_ANDES_V5=y
-CONFIG_SOC_RISCV_ANDES_AE350=y
+CONFIG_SOC_SERIES_ANDES_AE350=y
+CONFIG_SOC_ANDES_AE350=y
 CONFIG_BOARD_ADP_XC7K_AE350=y
 CONFIG_XIP=n
 CONFIG_CONSOLE=y

diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig
@@ -188,7 +188,7 @@ config HWINFO_GECKO
 config HWINFO_ANDES
 	bool "Andes system ID"
 	default y
-	depends on SOC_SERIES_RISCV_ANDES_V5
+	depends on SOC_FAMILY_ANDES_V5
 	help
 	  Enable Andes hwinfo driver
 

diff --git a/soc/riscv/andes_v5/CMakeLists.txt b/soc/riscv/andes_v5/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Nordic Semiconductor
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
diff --git a/soc/riscv/andes_v5/Kconfig b/soc/riscv/andes_v5/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_ANDES_V5
+	bool
+
+if SOC_FAMILY_ANDES_V5
+
+config SOC_FAMILY
+	string
+	default "andes_v5"
+
+source "soc/riscv/andes_v5/*/Kconfig.soc"
+
+endif # SOC_FAMILY_ANDES_V5
diff --git a/soc/riscv/andes_v5/Kconfig.defconfig b/soc/riscv/andes_v5/Kconfig.defconfig
@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/riscv/andes_v5/*/Kconfig.defconfig.series"
diff --git a/soc/riscv/andes_v5/Kconfig.soc b/soc/riscv/andes_v5/Kconfig.soc
@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "soc/riscv/andes_v5/*/Kconfig.series"
diff --git a/.../riscv-privileged/andes_v5/CMakeLists.txt → soc/riscv/andes_v5/ae350/CMakeLists.txt b/.../riscv-privileged/andes_v5/CMakeLists.txt → soc/riscv/andes_v5/ae350/CMakeLists.txt
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_include_directories(${CONFIG_SOC})
+zephyr_include_directories(.)
 
 zephyr_sources(
   start.S
@@ -24,6 +24,6 @@ if(CONFIG_SOC_ANDES_V5_EXECIT)
   zephyr_ld_options(-Wl,--mexecit)
 endif()
 
-if(CONFIG_SOC_RISCV_ANDES_AE350)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/ae350/linker.ld CACHE INTERNAL "")
+if(CONFIG_SOC_ANDES_AE350)
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
 endif()
diff --git a/...ivileged/andes_v5/Kconfig.defconfig.ae350 → ...cv/andes_v5/ae350/Kconfig.defconfig.ae350 b/...ivileged/andes_v5/Kconfig.defconfig.ae350 → ...cv/andes_v5/ae350/Kconfig.defconfig.ae350
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Andes Technology Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_RISCV_ANDES_AE350
+if SOC_ANDES_AE350
 
 config SOC
 	default "ae350"
@@ -25,4 +25,4 @@ config MP_MAX_NUM_CPUS
 	default 1
 	range 1 8
 
-endif # SOC_RISCV_ANDES_AE350
+endif # SOC_ANDES_AE350
diff --git a/...vileged/andes_v5/Kconfig.defconfig.series → ...v/andes_v5/ae350/Kconfig.defconfig.series b/...vileged/andes_v5/Kconfig.defconfig.series → ...v/andes_v5/ae350/Kconfig.defconfig.series
@@ -1,15 +1,15 @@
 # Copyright (c) 2021 Andes Technology Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-if SOC_SERIES_RISCV_ANDES_V5
+if SOC_SERIES_ANDES_AE350
 
 # Kconfig picks the first default with a satisfied condition.
 # SoC defaults should be parsed before SoC Series defaults, because SoCs usually
 # overrides SoC Series values.
-source "soc/riscv/riscv-privileged/andes_v5/Kconfig.defconfig.ae*"
+source "soc/riscv/andes_v5/ae350/Kconfig.defconfig.ae*"
 
 config SOC_SERIES
-	default "andes_v5"
+	default "ae350"
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 60000000
@@ -45,4 +45,4 @@ config MAX_IRQ_PER_AGGREGATOR
 config NUM_IRQS
 	default 64
 
-endif # SOC_SERIES_RISCV_ANDES_V5
+endif # SOC_SERIES_ANDES_AE350
diff --git a/soc/riscv/andes_v5/ae350/Kconfig.series b/soc/riscv/andes_v5/ae350/Kconfig.series
@@ -0,0 +1,11 @@
+# Copyright (c) 2021 Andes Technology Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_ANDES_AE350
+	bool "Andes V5 AE350 SoC Series Implementation"
+	select RISCV
+	select RISCV_PRIVILEGED
+	select RISCV_PRIVILEGED_STANDALONE
+	select SOC_FAMILY_ANDES_V5
+	help
+	  Enable support for Andes V5 AE350 SoC Series
diff --git a/...scv/riscv-privileged/andes_v5/Kconfig.soc → soc/riscv/andes_v5/ae350/Kconfig.soc b/...scv/riscv-privileged/andes_v5/Kconfig.soc → soc/riscv/andes_v5/ae350/Kconfig.soc
@@ -3,9 +3,9 @@
 
 choice
 prompt "Andes V5 SoC Selection"
-depends on SOC_SERIES_RISCV_ANDES_V5
+depends on SOC_SERIES_ANDES_AE350
 
-config SOC_RISCV_ANDES_AE350
+config SOC_ANDES_AE350
 	bool "Andes AE350 SoC implementation"
 	select ATOMIC_OPERATIONS_BUILTIN
 	select INCLUDE_RESET_VECTOR
@@ -18,7 +18,7 @@ config SOC_RISCV_ANDES_AE350
 
 endchoice
 
-if SOC_SERIES_RISCV_ANDES_V5
+if SOC_SERIES_ANDES_AE350
 
 choice
 prompt "Base CPU ISA options"
@@ -121,4 +121,4 @@ config SOC_ANDES_V5_IOCP
 		between cache and external non-caching master, such as DMA
 		controller.
 
-endif # SOC_SERIES_RISCV_ANDES_V5
+endif # SOC_SERIES_ANDES_AE350
diff --git a/...ivileged/andes_v5/common_linker/execit.ld → ...cv/andes_v5/ae350/common_linker/execit.ld b/...ivileged/andes_v5/common_linker/execit.ld → ...cv/andes_v5/ae350/common_linker/execit.ld
diff --git a/...privileged/andes_v5/common_linker/init.ld → ...iscv/andes_v5/ae350/common_linker/init.ld b/...privileged/andes_v5/common_linker/init.ld → ...iscv/andes_v5/ae350/common_linker/init.ld
diff --git a/...des_v5/common_linker/ram_start_nonzero.ld → .../ae350/common_linker/ram_start_nonzero.ld b/...des_v5/common_linker/ram_start_nonzero.ld → .../ae350/common_linker/ram_start_nonzero.ld
diff --git a/...iscv/riscv-privileged/andes_v5/l2_cache.c → soc/riscv/andes_v5/ae350/l2_cache.c b/...iscv/riscv-privileged/andes_v5/l2_cache.c → soc/riscv/andes_v5/ae350/l2_cache.c
diff --git a/...riscv-privileged/andes_v5/ae350/linker.ld → soc/riscv/andes_v5/ae350/linker.ld b/...riscv-privileged/andes_v5/ae350/linker.ld → soc/riscv/andes_v5/ae350/linker.ld
diff --git a/soc/riscv/riscv-privileged/andes_v5/pma.c → soc/riscv/andes_v5/ae350/pma.c b/soc/riscv/riscv-privileged/andes_v5/pma.c → soc/riscv/andes_v5/ae350/pma.c
diff --git a/...scv/riscv-privileged/andes_v5/ae350/soc.h → soc/riscv/andes_v5/ae350/soc.h b/...scv/riscv-privileged/andes_v5/ae350/soc.h → soc/riscv/andes_v5/ae350/soc.h
diff --git a/...v/riscv-privileged/andes_v5/soc_context.h → soc/riscv/andes_v5/ae350/soc_context.h b/...v/riscv-privileged/andes_v5/soc_context.h → soc/riscv/andes_v5/ae350/soc_context.h
diff --git a/...riscv/riscv-privileged/andes_v5/soc_irq.S → soc/riscv/andes_v5/ae350/soc_irq.S b/...riscv/riscv-privileged/andes_v5/soc_irq.S → soc/riscv/andes_v5/ae350/soc_irq.S
diff --git a/...v/riscv-privileged/andes_v5/soc_offsets.h → soc/riscv/andes_v5/ae350/soc_offsets.h b/...v/riscv-privileged/andes_v5/soc_offsets.h → soc/riscv/andes_v5/ae350/soc_offsets.h
diff --git a/soc/riscv/riscv-privileged/andes_v5/soc_v5.h → soc/riscv/andes_v5/ae350/soc_v5.h b/soc/riscv/riscv-privileged/andes_v5/soc_v5.h → soc/riscv/andes_v5/ae350/soc_v5.h
diff --git a/soc/riscv/riscv-privileged/andes_v5/start.S → soc/riscv/andes_v5/ae350/start.S b/soc/riscv/riscv-privileged/andes_v5/start.S → soc/riscv/andes_v5/ae350/start.S
diff --git a/soc/riscv/riscv-privileged/andes_v5/Kconfig.series b/soc/riscv/riscv-privileged/andes_v5/Kconfig.series