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doc: st: fix nucleo_h533re documentation
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1. Changing default ADC sens line for ch0 on PA0
- `adc1` was documented to be sensing ch14 on PB1.
- This seems impossible because of a conflict between ch14
and UART2.
- `adc1` node is not defined in the board's DTS.

2. Set SPI1 NSS pin to PA4
- hardware NSS signal was documented to output on PC9.
- PC9 cannot be assigned as HW NSS for SPI1.
- HW NSS on SPI1 is by default on PA4, and remapeable to PA15.

3. Update number of UART lines available
- There are a total of 7 U(S)ARTs available on this board.

(cherry picked from commit 12bb405)

Original-Signed-off-by: Alex Fabre <alex.fabre@rtone.fr>
GitOrigin-RevId: 12bb405
Change-Id: I8684703c41e8b6a0a51b857e9ddda6ce7440066b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/5666208
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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AlexFabre authored and Chromeos LUCI committed Jun 28, 2024
1 parent 33cacf4 commit faabf0e
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8 changes: 5 additions & 3 deletions boards/st/nucleo_h533re/doc/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -170,6 +170,8 @@ The Zephyr nucleo_h533re board configuration supports the following hardware fea
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported on this Zephyr port.

Expand Down Expand Up @@ -205,9 +207,9 @@ For more details please refer to `STM32H5 Nucleo-64 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------

- ADC1 channel 14 input: PB1
- ADC1 channel 0 input: PA0
- USART1 TX/RX : PB14/PB15 (Arduino USART1)
- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PC9
- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PA4
- UART2 TX/RX : PA2/PA3 (VCP)
- USER_PB : PC13

Expand All @@ -221,7 +223,7 @@ as well as main PLL clock. By default System clock is driven by PLL clock at
Serial Port
-----------

Nucleo H533RE board has up to 6 U(S)ARTs. The Zephyr console output is assigned
Nucleo H533RE board has up to 4 USARTs, 2 UARTs, and one LPUART. The Zephyr console output is assigned
to USART2. Default settings are 115200 8N1.

Programming and Debugging
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1 change: 1 addition & 0 deletions boards/st/nucleo_h533re/nucleo_h533re.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -14,4 +14,5 @@ supported:
- watchdog
- pwm
- rtc
- adc
vendor: st

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