Skip to content
View cpantel's full-sized avatar

Block or report cpantel

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. evilCodeSequence evilCodeSequence Public

    Forked from ciaa/icicle

    32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

    C 1

  2. VGARenderer VGARenderer Public

    Render VGA from the output of a Verilog or VHDL simulation

    Tcl 1

  3. prog_fpgas prog_fpgas Public

    The nexys4ddr (vivado) port of https://github.com/simonmonk/prog_fpgas (ISE)

    Verilog 1 1

  4. playground playground Public

    POCs, tips, recipes

    Shell 1

  5. Flash-via-SPI Flash-via-SPI Public

    Some experiments related to reading the flash memory of a broken router

    C 1

  6. Forzando-Brutalmente-MD5 Forzando-Brutalmente-MD5 Public

    C 6