MIPS

The implementation & virtualization of the MIPS computer architecture

"Computer-Aided Design" course project, IUST, Dr. Fazeli, Spring 2021

We've implemented 32-bit pipelined MIPS architecture by the Verilog hardware programming language. We've also virtualize 8-bit MIPS using Proteus with full functionality. All of the units include PC, Memory, Register File, ALU & other decoders do their work successfully.

We use this schema as the base architecture:

Some virtualization images:

Notes:

• There are several Verilog files in this project with the format .v. To run the whole project, you need to open the whole folder in some special softwares such as Xilinx.
• The virtualization files are in the folder Virtualization. You need to open these files with Proteus software.

Project contributors:

• Danial Bazmandeh, BSc, Computer Engineering
• Alireza Haghani, BSc, Computer Engineering
• Seyed Sina Ziaee, BSc, Computer Engineering