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digital-design-hq

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  1. Digital-Resources Digital-Resources Public

    53 5

  2. Example-Peripheral Example-Peripheral Public template

    SystemVerilog 2

  3. SPI-Master-Peripheral SPI-Master-Peripheral Public

    SystemVerilog 2

  4. Ethernet-Mac Ethernet-Mac Public

    SystemVerilog 1

  5. Addressable-LED-Controller-Peripheral Addressable-LED-Controller-Peripheral Public

    RISC V 32 peripheral to control addressable LED strips

    Verilog

  6. I2C-master-peripheral I2C-master-peripheral Public

    SystemVerilog

Repositories

Showing 9 of 9 repositories
  • Digital-Resources Public
    digital-design-hq/Digital-Resources’s past year of commit activity
    53 5 0 1 Updated Nov 9, 2021
  • grlib_uart_wrapper Public

    this module unwraps record typed ports and hides lib dependencies. ready to be instaniated in verilog

    digital-design-hq/grlib_uart_wrapper’s past year of commit activity
    0 BSD-3-Clause 0 0 0 Updated Feb 5, 2021
  • I2C-master-peripheral Public
    digital-design-hq/I2C-master-peripheral’s past year of commit activity
    SystemVerilog 0 0 0 0 Updated Sep 27, 2019
  • Example-Peripheral Public template
    digital-design-hq/Example-Peripheral’s past year of commit activity
    SystemVerilog 2 0 3 0 Updated Sep 24, 2019
  • Ethernet-Mac Public
    digital-design-hq/Ethernet-Mac’s past year of commit activity
    SystemVerilog 1 0 0 0 Updated Aug 28, 2019
  • Avalon-Adapter Public
    digital-design-hq/Avalon-Adapter’s past year of commit activity
    SystemVerilog 0 0 0 0 Updated Aug 28, 2019
  • Part-Library Public
    digital-design-hq/Part-Library’s past year of commit activity
    SystemVerilog 0 0 0 0 Updated Aug 28, 2019
  • SPI-Master-Peripheral Public
    digital-design-hq/SPI-Master-Peripheral’s past year of commit activity
    SystemVerilog 2 0 0 0 Updated Jul 22, 2019
  • Addressable-LED-Controller-Peripheral Public

    RISC V 32 peripheral to control addressable LED strips

    digital-design-hq/Addressable-LED-Controller-Peripheral’s past year of commit activity
    Verilog 0 0 0 0 Updated Jul 21, 2019

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