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Fix: First attemp to patch issue #19
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This commit enhances round-robin stage which now stores the last grant
if en falls down to 0 and the completion paths (R & B channels).
This maintain the granted driver until the end of the packet transmission
and so ensure no data interleaving will occur, making the masters harder
to develop.

Next commit will concern AW/AR channels
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@dpretet
dpretet committed Nov 21, 2024
1 parent 736f93f commit 54bbadc
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Showing 7 changed files with 416 additions and 44 deletions.
17 changes: 16 additions & 1 deletion rtl/axicb_mst_switch_rd.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,8 @@ module axicb_mst_switch_rd
///////////////////////////////////////////////////////////////////////////

logic arch_en;
logic arch_en_c;
logic arch_en_r;
logic [MST_NB -1:0] arch_req;
logic [MST_NB -1:0] arch_grant;

Expand Down Expand Up @@ -106,7 +108,20 @@ module axicb_mst_switch_rd

assign i_arready = arch_grant & {MST_NB{o_arready}};

assign arch_en = o_arvalid & o_arready;
assign arch_en_c = |i_arvalid & o_arready;

always @ (posedge aclk or negedge aresetn) begin
if (!aresetn) begin
arch_en_r <= '0;
end else if (srst) begin
arch_en_r <= '0;
end else begin
if (arch_grant=='0) arch_en_r <= 1'b1;
else arch_en_r <= 1'b0;
end
end

assign arch_en = arch_en_c | arch_en_r;

assign o_arch = (arch_grant[0]) ? i_arch[0*ARCH_W+:ARCH_W] :
(arch_grant[1]) ? i_arch[1*ARCH_W+:ARCH_W] :
Expand Down
17 changes: 16 additions & 1 deletion rtl/axicb_mst_switch_wr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -71,6 +71,8 @@ module axicb_mst_switch_wr
///////////////////////////////////////////////////////////////////////////

logic awch_en;
logic awch_en_c;
logic awch_en_r;
logic [MST_NB -1:0] awch_req;
logic [MST_NB -1:0] awch_grant;

Expand Down Expand Up @@ -117,7 +119,20 @@ module axicb_mst_switch_wr

assign i_awready = awch_grant & {MST_NB{o_awready & !wch_full}};

assign awch_en = o_awvalid & o_awready;
assign awch_en_c = |i_awvalid & o_awready;

always @ (posedge aclk or negedge aresetn) begin
if (!aresetn) begin
awch_en_r <= '0;
end else if (srst) begin
awch_en_r <= '0;
end else begin
if (awch_grant=='0) awch_en_r <= 1'b1;
else awch_en_r <= 1'b0;
end
end

assign awch_en = awch_en_c | awch_en_r;

assign o_awch = (awch_grant[0]) ? i_awch[0*AWCH_W+:AWCH_W] :
(awch_grant[1]) ? i_awch[1*AWCH_W+:AWCH_W] :
Expand Down
78 changes: 50 additions & 28 deletions rtl/axicb_round_robin_core.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,8 @@ module axicb_round_robin_core

logic [REQ_NB -1:0] mask;
logic [REQ_NB -1:0] masked;
logic [REQ_NB -1:0] grant_r;
logic [REQ_NB -1:0] grant_c;


///////////////////////////////////////////////////////////////////////////
Expand All @@ -95,19 +97,19 @@ module axicb_round_robin_core

// 2.1 handles first the reqs which fall into the mask
if (|masked) begin
if (masked[0]) grant = 4'b0001;
else if (masked[1]) grant = 4'b0010;
else if (masked[2]) grant = 4'b0100;
else if (masked[3]) grant = 4'b1000;
else grant = 4'b0000;
if (masked[0]) grant_c = 4'b0001;
else if (masked[1]) grant_c = 4'b0010;
else if (masked[2]) grant_c = 4'b0100;
else if (masked[3]) grant_c = 4'b1000;
else grant_c = 4'b0000;

// 2.2 if the mask doesn't match the reqs, uses the unmasked ones
end else begin
if (req[0]) grant = 4'b0001;
else if (req[1]) grant = 4'b0010;
else if (req[2]) grant = 4'b0100;
else if (req[3]) grant = 4'b1000;
else grant = 4'b0000;
if (req[0]) grant_c = 4'b0001;
else if (req[1]) grant_c = 4'b0010;
else if (req[2]) grant_c = 4'b0100;
else if (req[3]) grant_c = 4'b1000;
else grant_c = 4'b0000;
end
end

Expand All @@ -122,34 +124,54 @@ module axicb_round_robin_core

// 2.1 handles first the reqs which fall into the mask
if (|masked) begin
if (masked[0]) grant = 8'b00000001;
else if (masked[1]) grant = 8'b00000010;
else if (masked[2]) grant = 8'b00000100;
else if (masked[3]) grant = 8'b00001000;
else if (masked[4]) grant = 8'b00010000;
else if (masked[5]) grant = 8'b00100000;
else if (masked[6]) grant = 8'b01000000;
else if (masked[7]) grant = 8'b10000000;
else grant = 8'b00000000;
if (masked[0]) grant_c = 8'b00000001;
else if (masked[1]) grant_c = 8'b00000010;
else if (masked[2]) grant_c = 8'b00000100;
else if (masked[3]) grant_c = 8'b00001000;
else if (masked[4]) grant_c = 8'b00010000;
else if (masked[5]) grant_c = 8'b00100000;
else if (masked[6]) grant_c = 8'b01000000;
else if (masked[7]) grant_c = 8'b10000000;
else grant_c = 8'b00000000;

// 2.2 if the mask doesn't match the reqs, uses the unmasked ones
end else begin
if (req[0]) grant = 8'b00000001;
else if (req[1]) grant = 8'b00000010;
else if (req[2]) grant = 8'b00000100;
else if (req[3]) grant = 8'b00001000;
else if (req[4]) grant = 8'b00010000;
else if (req[5]) grant = 8'b00100000;
else if (req[6]) grant = 8'b01000000;
else if (req[7]) grant = 8'b10000000;
else grant = 8'b00000000;
if (req[0]) grant_c = 8'b00000001;
else if (req[1]) grant_c = 8'b00000010;
else if (req[2]) grant_c = 8'b00000100;
else if (req[3]) grant_c = 8'b00001000;
else if (req[4]) grant_c = 8'b00010000;
else if (req[5]) grant_c = 8'b00100000;
else if (req[6]) grant_c = 8'b01000000;
else if (req[7]) grant_c = 8'b10000000;
else grant_c = 8'b00000000;
end
end

end

endgenerate


always @ (posedge aclk or negedge aresetn) begin
if (~aresetn) begin
grant_r <= '1;
end else if (srst) begin
grant_r <= '1;
end else begin
if (en) begin
grant_r <= grant_c;
end
end
end

always @ (*) begin
if (en)
grant = grant_c;
else
grant = grant_r;
end

///////////////////////////////////////////////////////////////////////////
// Generate the next mask
///////////////////////////////////////////////////////////////////////////
Expand Down
17 changes: 16 additions & 1 deletion rtl/axicb_slv_switch_rd.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -74,6 +74,8 @@ module axicb_slv_switch_rd
logic [SLV_NB -1:0] slv_ar_targeted;

logic rch_en;
logic rch_en_c;
logic rch_en_r;
logic [SLV_NB -1:0] rch_req;
logic [SLV_NB -1:0] rch_grant;

Expand Down Expand Up @@ -255,7 +257,20 @@ module axicb_slv_switch_rd
.grant (rch_grant)
);

assign rch_en = i_rvalid & i_rready & i_rlast & rch_running;
assign rch_en_c = |o_rvalid & i_rready & |o_rlast & rch_running;

always @ (posedge aclk or negedge aresetn) begin
if (!aresetn) begin
rch_en_r <= '0;
end else if (srst) begin
rch_en_r <= '0;
end else begin
if (rch_grant=='0) rch_en_r <= 1'b1;
else rch_en_r <= 1'b0;
end
end

assign rch_en = rch_en_c | rch_en_r;

assign rch_req = o_rvalid;

Expand Down
17 changes: 16 additions & 1 deletion rtl/axicb_slv_switch_wr.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -83,6 +83,8 @@ module axicb_slv_switch_wr
logic [SLV_NB -1:0] slv_w_targeted;

logic bch_en;
logic bch_en_c;
logic bch_en_r;
logic [SLV_NB -1:0] bch_req;
logic [SLV_NB -1:0] bch_grant;

Expand Down Expand Up @@ -263,7 +265,20 @@ module axicb_slv_switch_wr
.grant (bch_grant)
);

assign bch_en = i_bvalid & i_bready & bch_mr_empty;
assign bch_en_c = |o_bvalid & i_bready & bch_mr_empty;

always @ (posedge aclk or negedge aresetn) begin
if (!aresetn) begin
bch_en_r <= '0;
end else if (srst) begin
bch_en_r <= '0;
end else begin
if (bch_grant=='0) bch_en_r <= 1'b1;
else bch_en_r <= 1'b0;
end
end

assign bch_en = bch_en_c | bch_en_r;

assign bch_req = o_bvalid;

Expand Down
50 changes: 38 additions & 12 deletions test/svut/axicb_crossbar_top_testbench.gtkw
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@@ -1,27 +1,34 @@
[*]
[*] GTKWave Analyzer v3.3.121 (w)1999-2024 BSI
[*] Mon Nov 11 20:06:39 2024
[*] Tue Nov 19 19:32:08 2024
[*]
[dumpfile] "/Users/damien/workspace/hdl/axi-crossbar/test/svut/axicb_crossbar_top_testbench.fst"
[dumpfile_mtime] "Mon Nov 11 19:58:40 2024"
[dumpfile_size] 6956586
[dumpfile_mtime] "Tue Nov 19 18:40:31 2024"
[dumpfile_size] 182679
[savefile] "/Users/damien/workspace/hdl/axi-crossbar/test/svut/axicb_crossbar_top_testbench.gtkw"
[timestart] 319652800
[timestart] 0
[size] 1440 900
[pos] -1 -26
*-17.001486 320166000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[pos] -1 -1
*-22.155149 9082000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] axicb_crossbar_top_testbench.
[treeopen] axicb_crossbar_top_testbench.dut.
[treeopen] axicb_crossbar_top_testbench.dut.switchs.
[treeopen] axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].
[treeopen] axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.
[treeopen] axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.
[treeopen] axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.rch_round_robin.
[treeopen] axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].
[treeopen] axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.
[treeopen] axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.
[treeopen] axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_round_robin.
[treeopen] axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_round_robin.P0_ON.
[treeopen] axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.rch_round_robin.P0_ON.
[sst_width] 253
[sst_width] 396
[signals_width] 184
[sst_expanded] 1
[sst_vpaned_height] 262
@200
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@29
axicb_crossbar_top_testbench.dut.aclk
@200
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@28
axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.rch_en
@200
Expand All @@ -48,7 +55,6 @@ axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switc
axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.rch_round_robin.P0_ON.rr_p0.mask[3:0]
axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.rch_round_robin.P0_ON.rr_p0.masked[3:0]
axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.rch_round_robin.P0_ON.rr_p0.req[3:0]
@23
axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.rch_round_robin.P0_ON.rr_p0.grant[3:0]
@200
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Expand All @@ -65,5 +71,25 @@ axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switc
(3)axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.o_rvalid[3:0]
(3)axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.o_rready[3:0]
(3)axicb_crossbar_top_testbench.dut.switchs.SLV_SWITCHS_GEN[0].slv_switch.slv_switch_rd.o_rlast[3:0]
@200
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-
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axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_en
axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_en_c
axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_en_r
@22
axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_grant[3:0]
axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_req[3:0]
axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.i_awready[3:0]
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axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_round_robin.en
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axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_round_robin.P0_ON.rr_p0.grant_c[3:0]
axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_round_robin.P0_ON.rr_p0.grant_r[3:0]
axicb_crossbar_top_testbench.dut.switchs.MST_SWITCHS_GEN[0].mst_switch.mst_switch_wr.awch_round_robin.grant[3:0]
[pattern_trace] 1
[pattern_trace] 0
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