Change: Don't interleave read completion anymore and just route

        back the data until RLAST assertion. Will ease OoO
        support when ID is constant across masters and release
        this particular AXI support while most masters don't
        support it (#9)

doc/issue9_strict_ordering_rules.md

@@ -0,0 +1,36 @@
+# Strict Ordering Rules Support
+
+## Overview
+
+The first implementation of the crossbar didn't ensure a correct ordering of write and read
+response. Indeed, in order to simplify the implementation, the slave switch module just forward
+request and completion in the order a master issues and a slave completes, whatever the ID used.
+This makes the completion routed back to the master out-of-order if the request used multiple times
+the same ID across two or more slaves which are not completing at the same pace. Moreover, this core
+has been designed for a RISCV processor which couldn't target multiple slaves because using a single
+RAM instance, and use always the same ID.
+
+To enhance the crossbar and its ordering rules support, this development will upgrade the slave
+switch module to ensure the completion ordering correct among the same ID queue.
+
+## Design Plan
+
+Each slave switch will now embbed a FIFO for each ID, as much FIFO than outstanding request
+supported, with a depth equals to the the number of outstanding request supported. This FIFO will
+store the slave index targeted by the requests using the same ID.
+
+While each master is identified by its unique ID Mask, the number of FIFO could be huge. Indeed,
+the user must extend the ID width and these extra bits would widely increase the possible ORs.
+So the slave switch slave will always decode/remove the mask to instance a minimum number of FIFOs.
+
+The switch will no more support completion interleaving, i.e. a read completion will be
+now completely routed-back the master until RLAST assertion. This feature is not so usefull
+and may be complicated to support for a master.
+
+The switch will no more use a round-robin arbitration to route-back the completion but simply
+empty the FIFO's ID one by one, in-order.
+
+## Verification
+
+- Use the existing testbench driving randomized request
+- Unleash master drivers to issue multiple consecutive outstanding requets with the same ID

rtl/axicb_slv_switch_rd.sv

@@ -173,7 +173,7 @@ module axicb_slv_switch_rd
     ///////////////////////////////////////////////////////////////////////////
 
     generate
-    // Gather ARID and ARLEN to pass them to the completion circuit returning
+    // Gather ARLEN and ARID to pass them to the completion circuit returning
     // the DECERR completion in case of misrouting
     if (AXI_SIGNALING>0)
     begin: AXI_SUPPORT
@@ -207,6 +207,9 @@ module axicb_slv_switch_rd
     );
 
 
+    // rch_running prevents mis-routed completion to be routed-back
+    // the corresponding master.
+    // rlen is the length of the mis-routed packet
     always @ (posedge aclk or negedge aresetn) begin
         if (!aresetn) begin
             rlen <= 8'h0;
@@ -252,7 +255,7 @@ module axicb_slv_switch_rd
         .grant   (rch_grant)
     );
 
-    assign rch_en = i_rvalid & i_rready & rch_running;
+    assign rch_en = i_rvalid & i_rready & i_rlast & rch_running;
 
     assign rch_req = o_rvalid;