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Second attemp to patch issue #19
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- Clean-up interfaces to always drive correct attributes values:
    - slv tied RESP/ID if FIFOs are ampty
    - mst tied ADDR if FIFOs are empty
- Rework round-robin enable control in slave switch to avoid combinatorial loop
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@dpretet
dpretet committed Nov 25, 2024
1 parent faef87e commit 938c804
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Showing 7 changed files with 1,459 additions and 111 deletions.
48 changes: 42 additions & 6 deletions rtl/axicb_mst_if.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -127,8 +127,13 @@ module axicb_mst_if
logic [ARCH_W -1:0] arch;
logic [RCH_W -1:0] rch;
logic rlast;
logic rlast_r;
logic [AXI_ADDR_W -1:0] awaddr;
logic [AXI_ADDR_W -1:0] araddr;
logic wlast_r;

logic [BCH_W -1:0] bch_f;
logic [RCH_W -1:0] rch_f;

generate

Expand Down Expand Up @@ -232,7 +237,7 @@ module axicb_mst_if
.rclk (o_aclk),
.rrst_n (o_aresetn),
.rinc (w_rinc),
.rdata ({o_wlast, wch}),
.rdata ({wlast_r, wch}),
.rempty (w_empty),
.arempty ()
);
Expand All @@ -241,6 +246,7 @@ module axicb_mst_if
assign w_winc = i_wvalid & ~w_full;

assign o_wvalid = ~w_empty;
assign o_wlast = (w_empty) ? 1'b0 : wlast_r;
assign w_rinc = ~w_empty & o_wready;

///////////////////////////////////////////////////////////////////////////
Expand All @@ -264,7 +270,7 @@ module axicb_mst_if
.rclk (i_aclk),
.rrst_n (i_aresetn),
.rinc (b_rinc),
.rdata (i_bch),
.rdata (bch_f),
.rempty (b_empty),
.arempty ()
);
Expand All @@ -273,6 +279,7 @@ module axicb_mst_if
assign b_winc = o_bvalid & ~b_full;

assign i_bvalid = ~b_empty;
assign i_bch = (b_empty) ? '0 : bch_f;
assign b_rinc = ~b_empty & i_bready;

///////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -328,7 +335,7 @@ module axicb_mst_if
.rclk (i_aclk),
.rrst_n (i_aresetn),
.rinc (r_rinc),
.rdata ({i_rlast, i_rch}),
.rdata ({rlast_r, rch_f}),
.rempty (r_empty),
.arempty ()
);
Expand All @@ -338,6 +345,20 @@ module axicb_mst_if

assign i_rvalid = ~r_empty;
assign r_rinc = ~r_empty & i_rready;
assign i_rlast = (r_empty) ? 1'b0 : rlast_r;

always @ (*) begin

// +2 = RESP width
i_rch[AXI_ID_W+2 +: (RCH_W-AXI_ID_W-2)] = rch_f[AXI_ID_W+2 +: (RCH_W-AXI_ID_W-2)];

// Tied off ID and RESP to ensure correct values
if (r_empty) begin
i_rch[0 +: (AXI_ID_W+2)] = '0;
end else begin
i_rch[0 +: (AXI_ID_W+2)] = rch_f[0 +: (AXI_ID_W+2)];
end
end


///////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -409,12 +430,13 @@ module axicb_mst_if
.data_in ({i_wlast, i_wch}),
.push (i_wvalid),
.full (w_full),
.data_out ({o_wlast, wch}),
.data_out ({wlast_r, wch}),
.pull (o_wready),
.empty (w_empty)
);
assign i_wready = ~w_full;
assign o_wvalid = ~w_empty;
assign o_wlast = (w_empty) ? 1'b0 : wlast_r;

///////////////////////////////////////////////////////////////////////////
// Write Response Channel
Expand All @@ -435,12 +457,13 @@ module axicb_mst_if
.data_in (bch),
.push (o_bvalid),
.full (b_full),
.data_out (i_bch),
.data_out (bch_f),
.pull (i_bready),
.empty (b_empty)
);

assign i_bvalid = ~b_empty;
assign i_bch = (b_empty) ? '0 : bch_f;
assign o_bready = ~b_full;

///////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -489,14 +512,27 @@ module axicb_mst_if
.data_in ({rlast, rch}),
.push (o_rvalid),
.full (r_full),
.data_out ({i_rlast,i_rch}),
.data_out ({rlast_r,rch_f}),
.pull (i_rready),
.empty (r_empty)
);

assign i_rvalid = ~r_empty;
assign i_rlast = (r_empty) ? 1'b0 : rlast_r;
assign o_rready = ~r_full;

always @ (*) begin

// +2 = RESP width
i_rch[AXI_ID_W+2 +: (RCH_W-AXI_ID_W-2)] = rch_f[AXI_ID_W+2 +: (RCH_W-AXI_ID_W-2)];

// Tied off ID and RESP to ensure correct values
if (r_empty) begin
i_rch[0 +: (AXI_ID_W+2)] = '0;
end else begin
i_rch[0 +: (AXI_ID_W+2)] = rch_f[0 +: (AXI_ID_W+2)];
end
end

///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
Expand Down
18 changes: 9 additions & 9 deletions rtl/axicb_round_robin_core.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -154,10 +154,10 @@ module axicb_round_robin_core


always @ (posedge aclk or negedge aresetn) begin
if (~aresetn) begin
grant_r <= '1;
if (!aresetn) begin
grant_r <= '0;
end else if (srst) begin
grant_r <= '1;
grant_r <= '0;
end else begin
if (en) begin
grant_r <= grant_c;
Expand All @@ -181,10 +181,10 @@ module axicb_round_robin_core

always @ (posedge aclk or negedge aresetn) begin

if (~aresetn) begin
mask <= {REQ_NB{1'b1}};
if (!aresetn) begin
mask <= '0;
end else if (srst) begin
mask <= {REQ_NB{1'b1}};
mask <= '0;
end else begin
if (en && |grant) begin
if (grant[0]) mask <= 4'b1110;
Expand All @@ -199,10 +199,10 @@ module axicb_round_robin_core

always @ (posedge aclk or negedge aresetn) begin

if (~aresetn) begin
mask <= {REQ_NB{1'b1}};
if (!aresetn) begin
mask <= '0;
end else if (srst) begin
mask <= {REQ_NB{1'b1}};
mask <= '0;
end else begin
if (en && |grant) begin
if (grant[0]) mask <= 8'b11111110;
Expand Down
43 changes: 37 additions & 6 deletions rtl/axicb_slv_if.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -121,11 +121,14 @@ module axicb_slv_if
///////////////////////////////////////////////////////////////////////////////

logic [AWCH_W -1:0] awch;
logic [AWCH_W -1:0] awch_f;
logic [WCH_W -1:0] wch;
logic [BCH_W -1:0] bch;
logic [ARCH_W -1:0] arch;
logic [AWCH_W -1:0] arch_f;
logic [RCH_W -1:0] rch;
logic wlast;
logic wlast_r;


///////////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -334,7 +337,7 @@ module axicb_slv_if
.rclk (o_aclk),
.rrst_n (o_aresetn),
.rinc (aw_rinc),
.rdata (o_awch),
.rdata (awch_f),
.rempty (aw_empty),
.arempty ()
);
Expand All @@ -343,6 +346,13 @@ module axicb_slv_if
assign aw_winc = i_awvalid & ~aw_full;

assign o_awvalid = ~aw_empty;

always @ (*) begin
o_awch[AXI_ADDR_W +: (AWCH_W-AXI_ADDR_W)] = awch_f[AXI_ADDR_W +: (AWCH_W-AXI_ADDR_W)];
// tied off AWADDR to avoid x in switches
o_awch[0 +: AXI_ADDR_W] = (aw_empty) ? '0 : awch_f[0 +: AXI_ADDR_W];;
end

assign aw_rinc = ~aw_empty & o_awready;

///////////////////////////////////////////////////////////////////////////
Expand All @@ -366,7 +376,7 @@ module axicb_slv_if
.rclk (o_aclk),
.rrst_n (o_aresetn),
.rinc (w_rinc),
.rdata ({o_wlast, o_wch}),
.rdata ({wlast_r, o_wch}),
.rempty (w_empty),
.arempty ()
);
Expand All @@ -375,6 +385,7 @@ module axicb_slv_if
assign w_winc = i_wvalid & ~w_full;

assign o_wvalid = ~w_empty;
assign o_wlast = (w_empty) ? 1'b0 : wlast_r;
assign w_rinc = ~w_empty & o_wready;

///////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -430,7 +441,7 @@ module axicb_slv_if
.rclk (o_aclk),
.rrst_n (o_aresetn),
.rinc (ar_rinc),
.rdata (o_arch),
.rdata (arch_f),
.rempty (ar_empty),
.arempty ()
);
Expand All @@ -441,6 +452,12 @@ module axicb_slv_if
assign o_arvalid = ~ar_empty;
assign ar_rinc = ~ar_empty & o_arready;

always @ (*) begin
o_arch[AXI_ADDR_W +: (ARCH_W-AXI_ADDR_W)] = arch_f[AXI_ADDR_W +: (ARCH_W-AXI_ADDR_W)];
// tied off ARADDR to avoid x in switches
o_arch[0 +: AXI_ADDR_W] = (ar_empty) ? '0 : arch_f[0 +: AXI_ADDR_W];;
end

///////////////////////////////////////////////////////////////////////////
// Read Data Channel
///////////////////////////////////////////////////////////////////////////
Expand Down Expand Up @@ -517,10 +534,17 @@ module axicb_slv_if
.data_in (awch),
.push (i_awvalid),
.full (aw_full),
.data_out (o_awch),
.data_out (awch_f),
.pull (o_awready),
.empty (aw_empty)
);

always @ (*) begin
o_awch[AXI_ADDR_W +: (AWCH_W-AXI_ADDR_W)] = awch_f[AXI_ADDR_W +: (AWCH_W-AXI_ADDR_W)];
// tied off AWADDR to avoid x in switches
o_awch[0 +: AXI_ADDR_W] = (aw_empty) ? '0 : awch_f[0 +: AXI_ADDR_W];;
end

assign i_awready = ~aw_full;
assign o_awvalid = ~aw_empty;

Expand All @@ -544,12 +568,13 @@ module axicb_slv_if
.data_in ({wlast, wch}),
.push (i_wvalid),
.full (w_full),
.data_out ({o_wlast, o_wch}),
.data_out ({wlast_r, o_wch}),
.pull (o_wready),
.empty (w_empty)
);
assign i_wready = ~w_full;
assign o_wvalid = ~w_empty;
assign o_wlast = (w_empty) ? 1'b0 : wlast_r;

///////////////////////////////////////////////////////////////////////////
// Write Response Channel
Expand Down Expand Up @@ -597,14 +622,20 @@ module axicb_slv_if
.data_in (arch),
.push (i_arvalid),
.full (ar_full),
.data_out (o_arch),
.data_out (arch_f),
.pull (o_arready),
.empty (ar_empty)
);

assign i_arready = ~ar_full;
assign o_arvalid = ~ar_empty;

always @ (*) begin
o_arch[AXI_ADDR_W +: (ARCH_W-AXI_ADDR_W)] = arch_f[AXI_ADDR_W +: (ARCH_W-AXI_ADDR_W)];
// tied off ARADDR to avoid x in switches
o_arch[0 +: AXI_ADDR_W] = (ar_empty) ? '0 : arch_f[0 +: AXI_ADDR_W];;
end

///////////////////////////////////////////////////////////////////////////
// Read Data Channel
///////////////////////////////////////////////////////////////////////////
Expand Down
20 changes: 16 additions & 4 deletions rtl/axicb_slv_switch_rd.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -74,8 +74,8 @@ module axicb_slv_switch_rd
logic [SLV_NB -1:0] slv_ar_targeted;

logic rch_en;
logic rch_en_c;
logic rch_en_r;
logic rfirst;
logic [SLV_NB -1:0] rch_req;
logic [SLV_NB -1:0] rch_grant;

Expand Down Expand Up @@ -257,8 +257,6 @@ module axicb_slv_switch_rd
.grant (rch_grant)
);

assign rch_en_c = |o_rvalid & i_rready & |o_rlast & rch_running;

always @ (posedge aclk or negedge aresetn) begin
if (!aresetn) begin
rch_en_r <= '0;
Expand All @@ -270,7 +268,21 @@ module axicb_slv_switch_rd
end
end

assign rch_en = rch_en_c | rch_en_r;
// Indicates the first read completion dataphase
always @ (posedge aclk or negedge aresetn) begin
if (!aresetn) begin
rfirst <= 1'b1;
end else if (srst) begin
rfirst <= 1'b1;
end else begin
if (i_rvalid && i_rready) begin
if (i_rlast) rfirst <= 1'b1;
else rfirst <= 1'b0;
end
end
end

assign rch_en = rfirst | rch_en_r;

assign rch_req = o_rvalid;

Expand Down
7 changes: 3 additions & 4 deletions rtl/axicb_switch_top.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,7 @@ module axicb_switch_top
parameter BCH_W = 8,
parameter ARCH_W = 8,
parameter RCH_W = 8
)(
) (
// Global interface
input wire aclk,
input wire aresetn,
Expand Down Expand Up @@ -323,10 +323,10 @@ module axicb_switch_top
///////////////////////////////////////////////////////////////////////////
// Reorder the valid/ready handshakes:
//
// slave interface uses awvalid[0,1,2,3,...] to target master interface 0,
// Slave interfaces use awvalid[0,1,2,3,...] to target master interface 0,
// master interface 1, master interface 2, master interface 3 ...
//
// master interfaces must receive awvalid[0] of slv_if0 + awvalid[0] of
// Master interfaces must receive awvalid[0] of slv_if0 + awvalid[0] of
// slv_if1 ...
//
// The same principle is applied for all channels targeted from slave
Expand Down Expand Up @@ -491,7 +491,6 @@ module axicb_switch_top
.o_data ({o_wlast[i], o_wch[i*WCH_W+:WCH_W]})
);


axicb_pipeline
#(
.DATA_BUS_W (BCH_W),
Expand Down
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