This project's goal is to build a simple microprocessor from basic logic components that were available in the late 80's to early 90's.
It uses a single-instruction architecture known as a Transport Triggered Architecture.
Feel free to ask questions by opening an issue!
The updated address decoder board is done. It uses an EPROM to decode the address bus to enable easy prototyping and experimenting, as the decoding logic can be generated by a software program, then burned into the EPROM. In an actual implementation, far simpler fixed-purpose logic would be used instead.
The address bus on the left is connected to the EPROM address inputs, and the EPROM outputs are connected to the terminal on the right. Each output can drive a read or write enable line, with the bank input allowing the transitioning of outputs to be aligned with different clock phases as needed.
Here's the module in a test harness to verify correct operation:
Next steps involve getting my toolchain for programming the EPROMs running again, and finishing the program to convert address maps into EPROM images.
Restarting this project with a little show-and-tell:
The board in the middle is the Program Counter Module, which serves four main functions:
- Increment the program address
- Allow the program address to be read to the data bus
- Allow the program address to be written to the data bus
- Coordinate reading and writing program memory
In the photo, the Program Counter Module is being tested using some switch and LED modules.
This project went dorment due to COVID and work issues, but I'm now in a position to start working on it again. Instead of directly building 3U Eurocard modules, I'm instead starting from smaller modules representing the main parts of the computer:
- ALU Module - Provides basic ALU functionality
- Program Memory Module - Provides program storage
- Program Counter Module - Basic program counter + R/W access
- Register File Module - Provides general purpose registers and ROM data
- Clock Module - Provides multi-phase clocks
- Initial Program Load Module - Provides initial bootstrapping, copying the monitor from ROM into program RAM
- Address Decoder Module - Activates read and write sockets
- Input Module - Dip Switches for data entry
- Output Module - Binary LED display for data readout
All of these stamps follow the Protonema stamp format.
This was the original (incomplete) design documentation for the TTAM implementation. This document will be updated over time to reflect the new approach being taken.
Design and Implementation Guide
- Documentation template contributed to the public domain by the Secure Scuttlebutt project: https://github.com/ssbc/scuttlebutt-protocol-guide
- Timing diagrams by https://github.com/wavedrom/wavedrom