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Issues: enjoy-digital/litex

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#614 opened Jul 31, 2020 by enjoy-digital
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248 Open 587 Closed
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Issues list

Disabling interrupts in bios for serial boot, re-enabling when files are uploaded completely.
#2149 opened Dec 23, 2024 by Rajnesh28
1
Combination of --toolchain=openxc7 and --no-compile-gateware options
#2141 opened Dec 16, 2024 by Mecrisp
Memory initialization files answered-waiting-feedback
#2136 opened Dec 11, 2024 by merveyubogluu
3
Wishbone adapter to access flash through a movable window answered-waiting-feedback
#2134 opened Dec 3, 2024 by NateMeyer
2
No compatibility with Efinity 2024.2.294
#2126 opened Nov 20, 2024 by m-byte
3
SPI "Manual Operation useful for Bulk transfers" seems to do nothing
#2124 opened Nov 11, 2024 by YusufCelik
1
CVA6 + Nexys4 DDR - RAM access issues
#2121 opened Nov 8, 2024 by juanschroeder
Video-terminal has useable Funtion?
#2112 opened Nov 4, 2024 by 2jack5657
litex_sim hangs when adding a call to a function in libliteeth
#2110 opened Oct 30, 2024 by jersey99
1
Implementing reset comming from the CPU jtag
#2109 opened Oct 28, 2024 by Dolu1990
Stuck at "liftoff" when I try romboot
#2108 opened Oct 27, 2024 by Stars-Collector
Cant have multiple Instances of Custom VHDL core
#2107 opened Oct 26, 2024 by Haron123
1
UartLite as a separate module.
#2096 opened Oct 15, 2024 by mohammadshahidzade
2
Generated Verilog project can't work
#2091 opened Oct 8, 2024 by snowprogrammer
2
RFC: Etherbone address detection
#2085 opened Sep 28, 2024 by m-byte
2
Simulate SoC and communicate through UART
#2084 opened Sep 28, 2024 by Leopard777
3
SPI flash not working with the ECP5 when using the Lattice Diamond toolchain
#2072 opened Sep 16, 2024 by dwalton65
Spi flash quad read not working with the ulx3s
#2064 opened Sep 11, 2024 by dwalton65
2
TIMER0 Interrupt
#2062 opened Sep 6, 2024 by gcourchinoux
3
Vexriscv SMP interrupts not working with Zephyr
#2061 opened Sep 6, 2024 by lcomino64
6
Can't choose apicula as toolchain
#2054 opened Aug 31, 2024 by nerfur
2
SoCBusHandler.add_peripheral does not work answered-waiting-feedback
#2052 opened Aug 29, 2024 by jwise
1
UART Core using add_uart in soc.py, Rare Transmission Error on first byte of sequence
#2049 opened Aug 24, 2024 by Haron123
Multi-bit Tristate has only single OE pin, and does not emit errors if you give it a bus
#2038 opened Aug 12, 2024 by jwise
2
Documentation Mismatch in I2CMaster Regarding Output Enable Behavior in bitbang.py
#2037 opened Aug 12, 2024 by Haron123
11
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