Add PLIC_X peripherals for esp32h2 (#265)

* Add PLIC_X peripherals for `esp32h2`

* Fix indent

esp32c6/src/plic_ux.rs

@@ -7,8 +7,9 @@ pub struct RegisterBlock {
     uxint_clear: UXINT_CLEAR,
     euip_status: EUIP_STATUS,
     uxint_pri: (),
-    _reserved5: [u8; 0x84],
+    _reserved5: [u8; 0x80],
     uxint_thresh: UXINT_THRESH,
+    uxint_claim: UXINT_CLAIM,
 }
 impl RegisterBlock {
     #[doc = "0x00 - PLIC UX Interrupt Enable Register"]
@@ -216,11 +217,16 @@ impl RegisterBlock {
     pub const fn uxint31_pri(&self) -> &UXINT_PRI {
         self.uxint_pri(31)
     }
-    #[doc = "0x94 - PLIC UX Interrupt Claim Register"]
+    #[doc = "0x90 - PLIC UX Interrupt Threshold Register"]
     #[inline(always)]
     pub const fn uxint_thresh(&self) -> &UXINT_THRESH {
         &self.uxint_thresh
     }
+    #[doc = "0x94 - PLIC UX Interrupt Claim Register"]
+    #[inline(always)]
+    pub const fn uxint_claim(&self) -> &UXINT_CLAIM {
+        &self.uxint_claim
+    }
 }
 #[doc = "UXINT_ENABLE (rw) register accessor: PLIC UX Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_enable`] module"]
 pub type UXINT_ENABLE = crate::Reg<uxint_enable::UXINT_ENABLE_SPEC>;
@@ -242,7 +248,11 @@ pub mod euip_status;
 pub type UXINT_PRI = crate::Reg<uxint_pri::UXINT_PRI_SPEC>;
 #[doc = "PLIC UX Interrupt %s Priority Register"]
 pub mod uxint_pri;
-#[doc = "UXINT_THRESH (rw) register accessor: PLIC UX Interrupt Claim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_thresh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_thresh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_thresh`] module"]
+#[doc = "UXINT_THRESH (rw) register accessor: PLIC UX Interrupt Threshold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_thresh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_thresh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_thresh`] module"]
 pub type UXINT_THRESH = crate::Reg<uxint_thresh::UXINT_THRESH_SPEC>;
-#[doc = "PLIC UX Interrupt Claim Register"]
+#[doc = "PLIC UX Interrupt Threshold Register"]
 pub mod uxint_thresh;
+#[doc = "UXINT_CLAIM (rw) register accessor: PLIC UX Interrupt Claim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_claim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_claim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_claim`] module"]
+pub type UXINT_CLAIM = crate::Reg<uxint_claim::UXINT_CLAIM_SPEC>;
+#[doc = "PLIC UX Interrupt Claim Register"]
+pub mod uxint_claim;

esp32c6/src/plic_ux/uxint_claim.rs

@@ -0,0 +1,48 @@
+#[doc = "Register `UXINT_CLAIM` reader"]
+pub type R = crate::R<UXINT_CLAIM_SPEC>;
+#[doc = "Register `UXINT_CLAIM` writer"]
+pub type W = crate::W<UXINT_CLAIM_SPEC>;
+#[doc = "Field `CPU_UXINT_CLAIM` reader - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."]
+pub type CPU_UXINT_CLAIM_R = crate::FieldReader<u32>;
+#[doc = "Field `CPU_UXINT_CLAIM` writer - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."]
+pub type CPU_UXINT_CLAIM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."]
+    #[inline(always)]
+    pub fn cpu_uxint_claim(&self) -> CPU_UXINT_CLAIM_R {
+        CPU_UXINT_CLAIM_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("UXINT_CLAIM")
+            .field("cpu_uxint_claim", &self.cpu_uxint_claim())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."]
+    #[inline(always)]
+    #[must_use]
+    pub fn cpu_uxint_claim(&mut self) -> CPU_UXINT_CLAIM_W<UXINT_CLAIM_SPEC> {
+        CPU_UXINT_CLAIM_W::new(self, 0)
+    }
+}
+#[doc = "PLIC UX Interrupt Claim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_claim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_claim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct UXINT_CLAIM_SPEC;
+impl crate::RegisterSpec for UXINT_CLAIM_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`uxint_claim::R`](R) reader structure"]
+impl crate::Readable for UXINT_CLAIM_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`uxint_claim::W`](W) writer structure"]
+impl crate::Writable for UXINT_CLAIM_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets UXINT_CLAIM to value 0"]
+impl crate::Resettable for UXINT_CLAIM_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

esp32c6/src/plic_ux/uxint_thresh.rs

@@ -2,34 +2,34 @@
 pub type R = crate::R<UXINT_THRESH_SPEC>;
 #[doc = "Register `UXINT_THRESH` writer"]
 pub type W = crate::W<UXINT_THRESH_SPEC>;
-#[doc = "Field `CPU_UXINT_CLAIM` reader - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."]
-pub type CPU_UXINT_CLAIM_R = crate::FieldReader<u32>;
-#[doc = "Field `CPU_UXINT_CLAIM` writer - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."]
-pub type CPU_UXINT_CLAIM_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+#[doc = "Field `CPU_UXINT_THRESH` reader - "]
+pub type CPU_UXINT_THRESH_R = crate::FieldReader;
+#[doc = "Field `CPU_UXINT_THRESH` writer - "]
+pub type CPU_UXINT_THRESH_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
 impl R {
-    #[doc = "Bits 0:31 - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."]
+    #[doc = "Bits 0:7"]
     #[inline(always)]
-    pub fn cpu_uxint_claim(&self) -> CPU_UXINT_CLAIM_R {
-        CPU_UXINT_CLAIM_R::new(self.bits)
+    pub fn cpu_uxint_thresh(&self) -> CPU_UXINT_THRESH_R {
+        CPU_UXINT_THRESH_R::new((self.bits & 0xff) as u8)
     }
 }
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
         f.debug_struct("UXINT_THRESH")
-            .field("cpu_uxint_claim", &self.cpu_uxint_claim())
+            .field("cpu_uxint_thresh", &self.cpu_uxint_thresh())
             .finish()
     }
 }
 impl W {
-    #[doc = "Bits 0:31 - hp_mb_int is generated after writing 32'h20200721 to core0_lp_intr_flag."]
+    #[doc = "Bits 0:7"]
     #[inline(always)]
     #[must_use]
-    pub fn cpu_uxint_claim(&mut self) -> CPU_UXINT_CLAIM_W<UXINT_THRESH_SPEC> {
-        CPU_UXINT_CLAIM_W::new(self, 0)
+    pub fn cpu_uxint_thresh(&mut self) -> CPU_UXINT_THRESH_W<UXINT_THRESH_SPEC> {
+        CPU_UXINT_THRESH_W::new(self, 0)
     }
 }
-#[doc = "PLIC UX Interrupt Claim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_thresh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_thresh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+#[doc = "PLIC UX Interrupt Threshold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_thresh::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_thresh::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct UXINT_THRESH_SPEC;
 impl crate::RegisterSpec for UXINT_THRESH_SPEC {
     type Ux = u32;

esp32c6/svd/patches/esp32c6.yaml

@@ -166,7 +166,7 @@ _add:
             bitOffset: 0
             bitWidth: 8
             access: read-write
-        UXINT_CLAIM:
+      UXINT_CLAIM:
         description: "PLIC UX Interrupt Claim Register"
         addressOffset: 0x0094
         size: 32

esp32h2/src/lib.rs

@@ -2755,6 +2755,98 @@ impl core::fmt::Debug for USB_DEVICE {
 }
 #[doc = "Full-speed USB Serial/JTAG Controller"]
 pub mod usb_device;
+#[doc = "PLIC Peripheral"]
+pub struct PLIC_MX {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for PLIC_MX {}
+impl PLIC_MX {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const plic_mx::RegisterBlock = 0x2000_1000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const plic_mx::RegisterBlock {
+        Self::PTR
+    }
+    #[doc = r" Steal an instance of this peripheral"]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = r" that may race with any existing instances, for example by only"]
+    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
+    #[doc = r" original peripheral and using critical sections to coordinate"]
+    #[doc = r" access between multiple new instances."]
+    #[doc = r""]
+    #[doc = r" Additionally, other software such as HALs may rely on only one"]
+    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = r" no stolen instances are passed to such software."]
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: PhantomData,
+        }
+    }
+}
+impl Deref for PLIC_MX {
+    type Target = plic_mx::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for PLIC_MX {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PLIC_MX").finish()
+    }
+}
+#[doc = "PLIC Peripheral"]
+pub mod plic_mx;
+#[doc = "PLIC Peripheral"]
+pub struct PLIC_UX {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for PLIC_UX {}
+impl PLIC_UX {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const plic_ux::RegisterBlock = 0x2000_1400 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const plic_ux::RegisterBlock {
+        Self::PTR
+    }
+    #[doc = r" Steal an instance of this peripheral"]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = r" that may race with any existing instances, for example by only"]
+    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
+    #[doc = r" original peripheral and using critical sections to coordinate"]
+    #[doc = r" access between multiple new instances."]
+    #[doc = r""]
+    #[doc = r" Additionally, other software such as HALs may rely on only one"]
+    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = r" no stolen instances are passed to such software."]
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: PhantomData,
+        }
+    }
+}
+impl Deref for PLIC_UX {
+    type Target = plic_ux::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for PLIC_UX {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PLIC_UX").finish()
+    }
+}
+#[doc = "PLIC Peripheral"]
+pub mod plic_ux;
 #[no_mangle]
 static mut DEVICE_PERIPHERALS: bool = false;
 #[doc = r" All the peripherals."]
@@ -2870,6 +2962,10 @@ pub struct Peripherals {
     pub UHCI0: UHCI0,
     #[doc = "USB_DEVICE"]
     pub USB_DEVICE: USB_DEVICE,
+    #[doc = "PLIC_MX"]
+    pub PLIC_MX: PLIC_MX,
+    #[doc = "PLIC_UX"]
+    pub PLIC_UX: PLIC_UX,
 }
 impl Peripherals {
     #[doc = r" Returns all the peripherals *once*."]
@@ -2947,6 +3043,8 @@ impl Peripherals {
             UART1: UART1::steal(),
             UHCI0: UHCI0::steal(),
             USB_DEVICE: USB_DEVICE::steal(),
+            PLIC_MX: PLIC_MX::steal(),
+            PLIC_UX: PLIC_UX::steal(),
         }
     }
 }