Add PLIC_X peripherals for esp32h2

esp32h2/src/lib.rs

@@ -2755,6 +2755,98 @@ impl core::fmt::Debug for USB_DEVICE {
 }
 #[doc = "Full-speed USB Serial/JTAG Controller"]
 pub mod usb_device;
+#[doc = "PLIC Peripheral"]
+pub struct PLIC_MX {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for PLIC_MX {}
+impl PLIC_MX {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const plic_mx::RegisterBlock = 0x2000_1000 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const plic_mx::RegisterBlock {
+        Self::PTR
+    }
+    #[doc = r" Steal an instance of this peripheral"]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = r" that may race with any existing instances, for example by only"]
+    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
+    #[doc = r" original peripheral and using critical sections to coordinate"]
+    #[doc = r" access between multiple new instances."]
+    #[doc = r""]
+    #[doc = r" Additionally, other software such as HALs may rely on only one"]
+    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = r" no stolen instances are passed to such software."]
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: PhantomData,
+        }
+    }
+}
+impl Deref for PLIC_MX {
+    type Target = plic_mx::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for PLIC_MX {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PLIC_MX").finish()
+    }
+}
+#[doc = "PLIC Peripheral"]
+pub mod plic_mx;
+#[doc = "PLIC Peripheral"]
+pub struct PLIC_UX {
+    _marker: PhantomData<*const ()>,
+}
+unsafe impl Send for PLIC_UX {}
+impl PLIC_UX {
+    #[doc = r"Pointer to the register block"]
+    pub const PTR: *const plic_ux::RegisterBlock = 0x2000_1400 as *const _;
+    #[doc = r"Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const plic_ux::RegisterBlock {
+        Self::PTR
+    }
+    #[doc = r" Steal an instance of this peripheral"]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = r" that may race with any existing instances, for example by only"]
+    #[doc = r" accessing read-only or write-only registers, or by consuming the"]
+    #[doc = r" original peripheral and using critical sections to coordinate"]
+    #[doc = r" access between multiple new instances."]
+    #[doc = r""]
+    #[doc = r" Additionally, other software such as HALs may rely on only one"]
+    #[doc = r" peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = r" no stolen instances are passed to such software."]
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: PhantomData,
+        }
+    }
+}
+impl Deref for PLIC_UX {
+    type Target = plic_ux::RegisterBlock;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
+impl core::fmt::Debug for PLIC_UX {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("PLIC_UX").finish()
+    }
+}
+#[doc = "PLIC Peripheral"]
+pub mod plic_ux;
 #[no_mangle]
 static mut DEVICE_PERIPHERALS: bool = false;
 #[doc = r" All the peripherals."]
@@ -2870,6 +2962,10 @@ pub struct Peripherals {
     pub UHCI0: UHCI0,
     #[doc = "USB_DEVICE"]
     pub USB_DEVICE: USB_DEVICE,
+    #[doc = "PLIC_MX"]
+    pub PLIC_MX: PLIC_MX,
+    #[doc = "PLIC_UX"]
+    pub PLIC_UX: PLIC_UX,
 }
 impl Peripherals {
     #[doc = r" Returns all the peripherals *once*."]
@@ -2947,6 +3043,8 @@ impl Peripherals {
             UART1: UART1::steal(),
             UHCI0: UHCI0::steal(),
             USB_DEVICE: USB_DEVICE::steal(),
+            PLIC_MX: PLIC_MX::steal(),
+            PLIC_UX: PLIC_UX::steal(),
         }
     }
 }

esp32h2/src/plic_mx.rs

@@ -0,0 +1,258 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    mxint_enable: MXINT_ENABLE,
+    mxint_type: MXINT_TYPE,
+    mxint_clear: MXINT_CLEAR,
+    emip_status: EMIP_STATUS,
+    mxint_pri: (),
+    _reserved5: [u8; 0x80],
+    mxint_thresh: MXINT_THRESH,
+    mxint_claim: MXINT_CLAIM,
+}
+impl RegisterBlock {
+    #[doc = "0x00 - PLIC MX Interrupt Enable Register"]
+    #[inline(always)]
+    pub const fn mxint_enable(&self) -> &MXINT_ENABLE {
+        &self.mxint_enable
+    }
+    #[doc = "0x04 - PLIC MX Interrupt Type Register"]
+    #[inline(always)]
+    pub const fn mxint_type(&self) -> &MXINT_TYPE {
+        &self.mxint_type
+    }
+    #[doc = "0x08 - PLIC MX Interrupt Clear Register"]
+    #[inline(always)]
+    pub const fn mxint_clear(&self) -> &MXINT_CLEAR {
+        &self.mxint_clear
+    }
+    #[doc = "0x0c - PLIC EMIP Status Register"]
+    #[inline(always)]
+    pub const fn emip_status(&self) -> &EMIP_STATUS {
+        &self.emip_status
+    }
+    #[doc = "0x10..0x90 - PLIC MX Interrupt %s Priority Register"]
+    #[inline(always)]
+    pub const fn mxint_pri(&self, n: usize) -> &MXINT_PRI {
+        #[allow(clippy::no_effect)]
+        [(); 32][n];
+        unsafe {
+            &*(self as *const Self)
+                .cast::<u8>()
+                .add(16)
+                .add(32 * n)
+                .cast()
+        }
+    }
+    #[doc = "Iterator for array of:"]
+    #[doc = "0x10..0x90 - PLIC MX Interrupt %s Priority Register"]
+    #[inline(always)]
+    pub fn mxint_pri_iter(&self) -> impl Iterator<Item = &MXINT_PRI> {
+        (0..32).map(move |n| unsafe {
+            &*(self as *const Self)
+                .cast::<u8>()
+                .add(16)
+                .add(32 * n)
+                .cast()
+        })
+    }
+    #[doc = "0x10 - PLIC MX Interrupt 0 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint0_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(0)
+    }
+    #[doc = "0x30 - PLIC MX Interrupt 1 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint1_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(1)
+    }
+    #[doc = "0x50 - PLIC MX Interrupt 2 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint2_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(2)
+    }
+    #[doc = "0x70 - PLIC MX Interrupt 3 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint3_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(3)
+    }
+    #[doc = "0x90 - PLIC MX Interrupt 4 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint4_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(4)
+    }
+    #[doc = "0xb0 - PLIC MX Interrupt 5 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint5_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(5)
+    }
+    #[doc = "0xd0 - PLIC MX Interrupt 6 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint6_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(6)
+    }
+    #[doc = "0xf0 - PLIC MX Interrupt 7 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint7_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(7)
+    }
+    #[doc = "0x110 - PLIC MX Interrupt 8 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint8_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(8)
+    }
+    #[doc = "0x130 - PLIC MX Interrupt 9 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint9_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(9)
+    }
+    #[doc = "0x150 - PLIC MX Interrupt 10 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint10_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(10)
+    }
+    #[doc = "0x170 - PLIC MX Interrupt 11 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint11_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(11)
+    }
+    #[doc = "0x190 - PLIC MX Interrupt 12 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint12_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(12)
+    }
+    #[doc = "0x1b0 - PLIC MX Interrupt 13 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint13_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(13)
+    }
+    #[doc = "0x1d0 - PLIC MX Interrupt 14 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint14_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(14)
+    }
+    #[doc = "0x1f0 - PLIC MX Interrupt 15 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint15_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(15)
+    }
+    #[doc = "0x210 - PLIC MX Interrupt 16 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint16_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(16)
+    }
+    #[doc = "0x230 - PLIC MX Interrupt 17 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint17_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(17)
+    }
+    #[doc = "0x250 - PLIC MX Interrupt 18 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint18_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(18)
+    }
+    #[doc = "0x270 - PLIC MX Interrupt 19 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint19_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(19)
+    }
+    #[doc = "0x290 - PLIC MX Interrupt 20 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint20_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(20)
+    }
+    #[doc = "0x2b0 - PLIC MX Interrupt 21 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint21_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(21)
+    }
+    #[doc = "0x2d0 - PLIC MX Interrupt 22 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint22_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(22)
+    }
+    #[doc = "0x2f0 - PLIC MX Interrupt 23 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint23_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(23)
+    }
+    #[doc = "0x310 - PLIC MX Interrupt 24 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint24_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(24)
+    }
+    #[doc = "0x330 - PLIC MX Interrupt 25 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint25_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(25)
+    }
+    #[doc = "0x350 - PLIC MX Interrupt 26 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint26_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(26)
+    }
+    #[doc = "0x370 - PLIC MX Interrupt 27 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint27_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(27)
+    }
+    #[doc = "0x390 - PLIC MX Interrupt 28 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint28_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(28)
+    }
+    #[doc = "0x3b0 - PLIC MX Interrupt 29 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint29_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(29)
+    }
+    #[doc = "0x3d0 - PLIC MX Interrupt 30 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint30_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(30)
+    }
+    #[doc = "0x3f0 - PLIC MX Interrupt 31 Priority Register"]
+    #[inline(always)]
+    pub const fn mxint31_pri(&self) -> &MXINT_PRI {
+        self.mxint_pri(31)
+    }
+    #[doc = "0x90 - PLIC MX Interrupt Threshold Register"]
+    #[inline(always)]
+    pub const fn mxint_thresh(&self) -> &MXINT_THRESH {
+        &self.mxint_thresh
+    }
+    #[doc = "0x94 - PLIC MX Interrupt Claim Register"]
+    #[inline(always)]
+    pub const fn mxint_claim(&self) -> &MXINT_CLAIM {
+        &self.mxint_claim
+    }
+}
+#[doc = "MXINT_ENABLE (rw) register accessor: PLIC MX Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_enable`] module"]
+pub type MXINT_ENABLE = crate::Reg<mxint_enable::MXINT_ENABLE_SPEC>;
+#[doc = "PLIC MX Interrupt Enable Register"]
+pub mod mxint_enable;
+#[doc = "MXINT_TYPE (rw) register accessor: PLIC MX Interrupt Type Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_type::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_type::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_type`] module"]
+pub type MXINT_TYPE = crate::Reg<mxint_type::MXINT_TYPE_SPEC>;
+#[doc = "PLIC MX Interrupt Type Register"]
+pub mod mxint_type;
+#[doc = "MXINT_CLEAR (rw) register accessor: PLIC MX Interrupt Clear Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_clear::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_clear::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_clear`] module"]
+pub type MXINT_CLEAR = crate::Reg<mxint_clear::MXINT_CLEAR_SPEC>;
+#[doc = "PLIC MX Interrupt Clear Register"]
+pub mod mxint_clear;
+#[doc = "EMIP_STATUS (r) register accessor: PLIC EMIP Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`emip_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emip_status`] module"]
+pub type EMIP_STATUS = crate::Reg<emip_status::EMIP_STATUS_SPEC>;
+#[doc = "PLIC EMIP Status Register"]
+pub mod emip_status;
+#[doc = "MXINT_PRI (rw) register accessor: PLIC MX Interrupt %s Priority Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_pri::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_pri::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_pri`] module"]
+pub type MXINT_PRI = crate::Reg<mxint_pri::MXINT_PRI_SPEC>;
+#[doc = "PLIC MX Interrupt %s Priority Register"]
+pub mod mxint_pri;
+#[doc = "MXINT_THRESH (rw) register accessor: PLIC MX Interrupt Threshold Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_thresh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_thresh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_thresh`] module"]
+pub type MXINT_THRESH = crate::Reg<mxint_thresh::MXINT_THRESH_SPEC>;
+#[doc = "PLIC MX Interrupt Threshold Register"]
+pub mod mxint_thresh;
+#[doc = "MXINT_CLAIM (rw) register accessor: PLIC MX Interrupt Claim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_claim::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_claim::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_claim`] module"]
+pub type MXINT_CLAIM = crate::Reg<mxint_claim::MXINT_CLAIM_SPEC>;
+#[doc = "PLIC MX Interrupt Claim Register"]
+pub mod mxint_claim;