Add the CLINT peripheral for ESP32-C6 and ESP32-H2

esp32c6/src/clint.rs

@@ -0,0 +1,89 @@
+#[repr(C)]
+#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
+#[doc = "Register block"]
+pub struct RegisterBlock {
+    _reserved0: [u8; 0x1800],
+    msip: MSIP,
+    mtimectl: MTIMECTL,
+    mtime: MTIME,
+    mtimecmp: MTIMECMP,
+    _reserved4: [u8; 0x03e8],
+    usip: USIP,
+    utimectl: UTIMECTL,
+    utime: UTIME,
+    utimecmp: UTIMECMP,
+}
+impl RegisterBlock {
+    #[doc = "0x1800 - "]
+    #[inline(always)]
+    pub const fn msip(&self) -> &MSIP {
+        &self.msip
+    }
+    #[doc = "0x1804 - "]
+    #[inline(always)]
+    pub const fn mtimectl(&self) -> &MTIMECTL {
+        &self.mtimectl
+    }
+    #[doc = "0x1808..0x1810 - "]
+    #[inline(always)]
+    pub const fn mtime(&self) -> &MTIME {
+        &self.mtime
+    }
+    #[doc = "0x1810..0x1818 - "]
+    #[inline(always)]
+    pub const fn mtimecmp(&self) -> &MTIMECMP {
+        &self.mtimecmp
+    }
+    #[doc = "0x1c00 - "]
+    #[inline(always)]
+    pub const fn usip(&self) -> &USIP {
+        &self.usip
+    }
+    #[doc = "0x1c04 - "]
+    #[inline(always)]
+    pub const fn utimectl(&self) -> &UTIMECTL {
+        &self.utimectl
+    }
+    #[doc = "0x1c08..0x1c10 - "]
+    #[inline(always)]
+    pub const fn utime(&self) -> &UTIME {
+        &self.utime
+    }
+    #[doc = "0x1c10..0x1c18 - "]
+    #[inline(always)]
+    pub const fn utimecmp(&self) -> &UTIMECMP {
+        &self.utimecmp
+    }
+}
+#[doc = "MSIP (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`msip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msip`] module"]
+pub type MSIP = crate::Reg<msip::MSIP_SPEC>;
+#[doc = ""]
+pub mod msip;
+#[doc = "MTIMECTL (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`mtimectl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimectl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimectl`] module"]
+pub type MTIMECTL = crate::Reg<mtimectl::MTIMECTL_SPEC>;
+#[doc = ""]
+pub mod mtimectl;
+#[doc = "MTIME (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`mtime::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtime`] module"]
+pub type MTIME = crate::Reg<mtime::MTIME_SPEC>;
+#[doc = ""]
+pub mod mtime;
+#[doc = "MTIMECMP (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`mtimecmp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtimecmp`] module"]
+pub type MTIMECMP = crate::Reg<mtimecmp::MTIMECMP_SPEC>;
+#[doc = ""]
+pub mod mtimecmp;
+#[doc = "USIP (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`usip::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usip::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usip`] module"]
+pub type USIP = crate::Reg<usip::USIP_SPEC>;
+#[doc = ""]
+pub mod usip;
+#[doc = "UTIMECTL (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`utimectl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`utimectl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@utimectl`] module"]
+pub type UTIMECTL = crate::Reg<utimectl::UTIMECTL_SPEC>;
+#[doc = ""]
+pub mod utimectl;
+#[doc = "UTIME (r) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`utime::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@utime`] module"]
+pub type UTIME = crate::Reg<utime::UTIME_SPEC>;
+#[doc = ""]
+pub mod utime;
+#[doc = "UTIMECMP (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`utimecmp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`utimecmp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@utimecmp`] module"]
+pub type UTIMECMP = crate::Reg<utimecmp::UTIMECMP_SPEC>;
+#[doc = ""]
+pub mod utimecmp;

esp32c6/src/clint/msip.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `MSIP` reader"]
+pub type R = crate::R<MSIP_SPEC>;
+#[doc = "Register `MSIP` writer"]
+pub type W = crate::W<MSIP_SPEC>;
+#[doc = "Field `MSIP` reader - Configures the pending status of the machine software interrupt."]
+pub type MSIP_R = crate::BitReader;
+#[doc = "Field `MSIP` writer - Configures the pending status of the machine software interrupt."]
+pub type MSIP_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Configures the pending status of the machine software interrupt."]
+    #[inline(always)]
+    pub fn msip(&self) -> MSIP_R {
+        MSIP_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MSIP").field("msip", &self.msip()).finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Configures the pending status of the machine software interrupt."]
+    #[inline(always)]
+    #[must_use]
+    pub fn msip(&mut self) -> MSIP_W<MSIP_SPEC> {
+        MSIP_W::new(self, 0)
+    }
+}
+#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`msip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MSIP_SPEC;
+impl crate::RegisterSpec for MSIP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`msip::R`](R) reader structure"]
+impl crate::Readable for MSIP_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`msip::W`](W) writer structure"]
+impl crate::Writable for MSIP_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets MSIP to value 0"]
+impl crate::Resettable for MSIP_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

esp32c6/src/clint/mtime.rs

@@ -0,0 +1,48 @@
+#[doc = "Register `MTIME` reader"]
+pub type R = crate::R<MTIME_SPEC>;
+#[doc = "Register `MTIME` writer"]
+pub type W = crate::W<MTIME_SPEC>;
+#[doc = "Field `MTIME` reader - Configures the 64-bit CLINT timer counter value."]
+pub type MTIME_R = crate::FieldReader<u64>;
+#[doc = "Field `MTIME` writer - Configures the 64-bit CLINT timer counter value."]
+pub type MTIME_W<'a, REG> = crate::FieldWriter<'a, REG, 64, u64>;
+impl R {
+    #[doc = "Bits 0:63 - Configures the 64-bit CLINT timer counter value."]
+    #[inline(always)]
+    pub fn mtime(&self) -> MTIME_R {
+        MTIME_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MTIME")
+            .field("mtime", &self.mtime())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:63 - Configures the 64-bit CLINT timer counter value."]
+    #[inline(always)]
+    #[must_use]
+    pub fn mtime(&mut self) -> MTIME_W<MTIME_SPEC> {
+        MTIME_W::new(self, 0)
+    }
+}
+#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`mtime::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtime::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MTIME_SPEC;
+impl crate::RegisterSpec for MTIME_SPEC {
+    type Ux = u64;
+}
+#[doc = "`read()` method returns [`mtime::R`](R) reader structure"]
+impl crate::Readable for MTIME_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`mtime::W`](W) writer structure"]
+impl crate::Writable for MTIME_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u64 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u64 = 0;
+}
+#[doc = "`reset()` method sets MTIME to value 0"]
+impl crate::Resettable for MTIME_SPEC {
+    const RESET_VALUE: u64 = 0;
+}

esp32c6/src/clint/mtimecmp.rs

@@ -0,0 +1,48 @@
+#[doc = "Register `MTIMECMP` reader"]
+pub type R = crate::R<MTIMECMP_SPEC>;
+#[doc = "Register `MTIMECMP` writer"]
+pub type W = crate::W<MTIMECMP_SPEC>;
+#[doc = "Field `MTIMECMP` reader - Configures the 64-bit machine timer compare value."]
+pub type MTIMECMP_R = crate::FieldReader<u64>;
+#[doc = "Field `MTIMECMP` writer - Configures the 64-bit machine timer compare value."]
+pub type MTIMECMP_W<'a, REG> = crate::FieldWriter<'a, REG, 64, u64>;
+impl R {
+    #[doc = "Bits 0:63 - Configures the 64-bit machine timer compare value."]
+    #[inline(always)]
+    pub fn mtimecmp(&self) -> MTIMECMP_R {
+        MTIMECMP_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MTIMECMP")
+            .field("mtimecmp", &self.mtimecmp())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:63 - Configures the 64-bit machine timer compare value."]
+    #[inline(always)]
+    #[must_use]
+    pub fn mtimecmp(&mut self) -> MTIMECMP_W<MTIMECMP_SPEC> {
+        MTIMECMP_W::new(self, 0)
+    }
+}
+#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`mtimecmp::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimecmp::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MTIMECMP_SPEC;
+impl crate::RegisterSpec for MTIMECMP_SPEC {
+    type Ux = u64;
+}
+#[doc = "`read()` method returns [`mtimecmp::R`](R) reader structure"]
+impl crate::Readable for MTIMECMP_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`mtimecmp::W`](W) writer structure"]
+impl crate::Writable for MTIMECMP_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u64 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u64 = 0;
+}
+#[doc = "`reset()` method sets MTIMECMP to value 0"]
+impl crate::Resettable for MTIMECMP_SPEC {
+    const RESET_VALUE: u64 = 0;
+}

esp32c6/src/clint/mtimectl.rs

@@ -0,0 +1,88 @@
+#[doc = "Register `MTIMECTL` reader"]
+pub type R = crate::R<MTIMECTL_SPEC>;
+#[doc = "Register `MTIMECTL` writer"]
+pub type W = crate::W<MTIMECTL_SPEC>;
+#[doc = "Field `MTCE` reader - Configures whether to enable the CLINT timer counter."]
+pub type MTCE_R = crate::BitReader;
+#[doc = "Field `MTCE` writer - Configures whether to enable the CLINT timer counter."]
+pub type MTCE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MTIE` reader - Write 1 to enable the machine timer interrupt."]
+pub type MTIE_R = crate::BitReader;
+#[doc = "Field `MTIE` writer - Write 1 to enable the machine timer interrupt."]
+pub type MTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MTIP` reader - Represents the pending status of the machine timer interrupt."]
+pub type MTIP_R = crate::BitReader;
+#[doc = "Field `MTOF` reader - Configures whether the machine timer overflows."]
+pub type MTOF_R = crate::BitReader;
+#[doc = "Field `MTOF` writer - Configures whether the machine timer overflows."]
+pub type MTOF_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Configures whether to enable the CLINT timer counter."]
+    #[inline(always)]
+    pub fn mtce(&self) -> MTCE_R {
+        MTCE_R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write 1 to enable the machine timer interrupt."]
+    #[inline(always)]
+    pub fn mtie(&self) -> MTIE_R {
+        MTIE_R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Represents the pending status of the machine timer interrupt."]
+    #[inline(always)]
+    pub fn mtip(&self) -> MTIP_R {
+        MTIP_R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Configures whether the machine timer overflows."]
+    #[inline(always)]
+    pub fn mtof(&self) -> MTOF_R {
+        MTOF_R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MTIMECTL")
+            .field("mtce", &self.mtce())
+            .field("mtie", &self.mtie())
+            .field("mtip", &self.mtip())
+            .field("mtof", &self.mtof())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Configures whether to enable the CLINT timer counter."]
+    #[inline(always)]
+    #[must_use]
+    pub fn mtce(&mut self) -> MTCE_W<MTIMECTL_SPEC> {
+        MTCE_W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Write 1 to enable the machine timer interrupt."]
+    #[inline(always)]
+    #[must_use]
+    pub fn mtie(&mut self) -> MTIE_W<MTIMECTL_SPEC> {
+        MTIE_W::new(self, 1)
+    }
+    #[doc = "Bit 3 - Configures whether the machine timer overflows."]
+    #[inline(always)]
+    #[must_use]
+    pub fn mtof(&mut self) -> MTOF_W<MTIMECTL_SPEC> {
+        MTOF_W::new(self, 3)
+    }
+}
+#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`mtimectl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimectl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MTIMECTL_SPEC;
+impl crate::RegisterSpec for MTIMECTL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`mtimectl::R`](R) reader structure"]
+impl crate::Readable for MTIMECTL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`mtimectl::W`](W) writer structure"]
+impl crate::Writable for MTIMECTL_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets MTIMECTL to value 0"]
+impl crate::Resettable for MTIMECTL_SPEC {
+    const RESET_VALUE: u32 = 0;
+}

esp32c6/src/clint/usip.rs

@@ -0,0 +1,46 @@
+#[doc = "Register `USIP` reader"]
+pub type R = crate::R<USIP_SPEC>;
+#[doc = "Register `USIP` writer"]
+pub type W = crate::W<USIP_SPEC>;
+#[doc = "Field `USIP` reader - Configures the pending status of the user software interrupt."]
+pub type USIP_R = crate::BitReader;
+#[doc = "Field `USIP` writer - Configures the pending status of the user software interrupt."]
+pub type USIP_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Configures the pending status of the user software interrupt."]
+    #[inline(always)]
+    pub fn usip(&self) -> USIP_R {
+        USIP_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("USIP").field("usip", &self.usip()).finish()
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Configures the pending status of the user software interrupt."]
+    #[inline(always)]
+    #[must_use]
+    pub fn usip(&mut self) -> USIP_W<USIP_SPEC> {
+        USIP_W::new(self, 0)
+    }
+}
+#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`usip::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usip::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct USIP_SPEC;
+impl crate::RegisterSpec for USIP_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`usip::R`](R) reader structure"]
+impl crate::Readable for USIP_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`usip::W`](W) writer structure"]
+impl crate::Writable for USIP_SPEC {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets USIP to value 0"]
+impl crate::Resettable for USIP_SPEC {
+    const RESET_VALUE: u32 = 0;
+}