JSON encoder and decoder in SystemVerilog

The project introduces JSON decoder and encoder implementation in pure SystemVerilog without any external dependencies. It provides SystemVerilog package json_pkg for convenient integration into any HDL project.

The package allows decoding and encoding JSON values from or to string (file). It also provides rich capabilities for values manipulation, traversing ans inspection. Special interface classes can be used for creation of encoding-friendly user classes. Additionally, there is an error propagation and reporting system inspired by some ideas of Rust.

Implementation follows ECMA standard almost completely - only several cases of escape values are not supported.

Code tested intensively in Verilator 5.24 with SVUnit using JSONTestSuite and custom tests. Support of other simulators is planned, but not guaranteed at the moment.

Documentation

Documentation is hosted at Github Pages.

All documentation is written in Asciidoc and transformed into static site via Antora.

Integration

• Setup environment variable SVJSON_ROOT with a path to svjson root on your filesystem

• Add filelist to your simulator using according arguments, e.g. -f ${SVJSON_ROOT}/src/filelist.f

• Use classes within package to decode or encode JSON files: json_pkg::json_decoder::load_file() or json_pkg::json_encoder::dump_file()

For more details please refer to documentation.

Development

Please refer to developer guide in documentation.