-
15:10
(UTC +05:30) - in/fayizferosh
Popular repositories Loading
-
yosys-tcl-ui-report
yosys-tcl-ui-report Public5 Day TCL begginer to advanced training workshop by VSD
-
soc-design-and-planning-nasscom-vsd
soc-design-and-planning-nasscom-vsd Public2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advanced Physical Design using OpenLANE/Sky130)
-
advanced-pd-using-openlane-sky130
advanced-pd-using-openlane-sky130 Public2 Week Advanced Physical Design using OpenLANE/Sky130 workshop with complete RTL2GDSII flow organised by VSD as part of Level-3 of Chip Design for High School Program in collaboration with Intel India
Verilog 3
-
btech-mini-project
btech-mini-project PublicThis was my BTech degree Mini-Project during semester 5 and it is an electronic lock which can be unlocked from anywhere.
HTML 1
-
risc-v-myth-report
risc-v-myth-report Public5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD
Verilog
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.