logging, minor

fedex81 · Oct 28, 2023 · f9eadda · f9eadda
1 parent eee14da
commit f9eadda
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Showing 6 changed files with 21 additions and 13 deletions.
diff --git a/src/main/java/omegadrive/bus/md/GenesisBus.java b/src/main/java/omegadrive/bus/md/GenesisBus.java
@@ -29,7 +29,6 @@
 import omegadrive.cart.mapper.RomMapper;
 import omegadrive.cart.mapper.md.ExSsfMapper;
 import omegadrive.cart.mapper.md.MdBackupMemoryMapper;
-import omegadrive.cart.mapper.md.MdT5740Mapper;
 import omegadrive.cart.mapper.md.Ssf2Mapper;
 import omegadrive.cpu.z80.Z80Provider;
 import omegadrive.joypad.GenesisJoypad;
@@ -53,6 +52,7 @@
 import static omegadrive.cpu.m68k.M68kProvider.MD_PC_MASK;
 import static omegadrive.joypad.JoypadProvider.JoypadType.BUTTON_3;
 import static omegadrive.system.SystemProvider.SystemEvent.FORCE_PAD_TYPE;
+import static omegadrive.util.LogHelper.logWarnOnce;
 import static omegadrive.util.Util.th;
 
 public class GenesisBus extends DeviceAwareBus<GenesisVdpProvider, GenesisJoypad> implements GenesisBusProvider, RomMapper {
@@ -214,7 +214,7 @@ public int readData(int address, final Size size) {
             checkBackupMemoryMapper(SramMode.READ_WRITE);
             data = mapper.readData(address, size);
         } else {
-            LOG.error("Unexpected bus read: {}, 68k PC: {}",
+            logWarnOnce(LOG, "Unexpected bus read: {}, 68k PC: {}",
                     th(address), th(m68kProvider.getPC()));
             data = size.getMask();
         }
@@ -255,14 +255,13 @@ private void cartWrite(int addressL, int data, Size size) {
             return;
         }
         //Batman&Robin writes to address 0 - tries to enable debug mode?
-        LOG.warn("Unexpected write to ROM address {}, value {} {}", th(addressL),
+        logWarnOnce(LOG, "Unexpected write to ROM address {}, value {} {}", th(addressL),
                 th(data), size);
     }
 
     private void reservedWrite(int addressL, int data, Size size) {
         if (msuMdHandler == MsuMdHandler.NO_OP_HANDLER) {
-            LOG.error("Unexpected bus write: {}, data {} {}, 68k PC: {}",
-                    th(addressL), th(data), size,
+            logWarnOnce(LOG, "Unexpected bus write: {}, 68k PC: {}", th(addressL),
                     th(m68kProvider.getPC()));
         } else {
             msuMdHandler.handleMsuMdWrite(addressL, data, size);
@@ -271,7 +270,7 @@ private void reservedWrite(int addressL, int data, Size size) {
 
     private int reservedRead(int address, Size size) {
         if (msuMdHandler == MsuMdHandler.NO_OP_HANDLER) {
-            LOG.warn("Read on reserved address: {}, {}", th(address), size);
+            logWarnOnce(LOG, "Read on reserved address: {}, {}", th(address), size);
             return size.getMax();
         } else {
             //reads rom at 0x40_0000 MegaCD mirror
@@ -599,7 +598,7 @@ private void ioWriteInternal(int addressL, int dataL, Size size) {
                 break;
             default:
                 if (address >= 0xE && address < 0x20) {
-                    LOG.info("Write serial control: {}, data: {} {}", th(addressL), th(data), size);
+                    logWarnOnce(LOG, "Write serial control: {}", th(addressL));
                     Util.writeData(serialPortData, size, address - 0xE, data);
                 } else { //Reserved
                     LOG.error("Unexpected ioWrite {}, data {}", th(addressL), th(data));
@@ -642,7 +641,7 @@ private int z80MemoryRead(int address, Size size) {
     private void z80MemoryWrite(int address, Size size, int dataL) {
         busArbiter.addCyclePenalty(BusArbiter.CpuType.M68K, M68K_CYCLE_PENALTY);
         if (!z80BusRequested || z80ResetState) {
-            LOG.warn("68k write access to Z80 bus with busreq: {}, z80reset: {}", z80BusRequested, z80ResetState);
+            logWarnOnce(LOG, "68k write access to Z80 bus with busreq: {}, z80reset: {}", z80BusRequested, z80ResetState);
             return;
         }
         address &= GenesisBusProvider.M68K_TO_Z80_MEMORY_MASK;

diff --git a/src/main/java/omegadrive/bus/md/GenesisZ80BusProviderImpl.java b/src/main/java/omegadrive/bus/md/GenesisZ80BusProviderImpl.java
@@ -30,6 +30,7 @@
 import omegadrive.util.Size;
 import org.slf4j.Logger;
 
+import static omegadrive.util.LogHelper.logWarnOnce;
 import static omegadrive.util.Util.th;
 
 public class GenesisZ80BusProviderImpl extends DeviceAwareBus implements GenesisZ80BusProvider {
@@ -81,7 +82,7 @@ public int read(final int address, final Size size) {
                 data = getFm().read();
             }
         } else if (address >= START_ROM_BANK_ADDRESS && address <= END_UNUSED) {
-            LOG.warn("Z80 read bank switching/unused: {}", th(address));
+            logWarnOnce(LOG, "Z80 read bank switching/unused: {}", th(address));
         } else if (address >= START_VDP && address <= END_VDP_VALID) {
             int vdpAddress = (VDP_BASE_ADDRESS + address);
             if (verbose) LOG.info("Z80 read VDP memory , address {}", th(address));

diff --git a/src/main/java/omegadrive/vdp/md/GenesisVdp.java b/src/main/java/omegadrive/vdp/md/GenesisVdp.java
@@ -396,8 +396,7 @@ private void updateStateFromControlPortWrite(boolean isRegisterWrite, int data)
     protected void writeDataPortInternal(int data) {
         writePendingControlPort = false;
         if (vramMode == null) {
-            LOG.warn("Invalid writeDataPort, vramMode {}, data: {}, address: {}",
-                    vramMode, th(data), th(addressRegister));
+            logWarnOnce(LOG, "Invalid writeDataPort, vramMode: null");
         }
         fifoPush(addressRegister, data);
         addressRegister += autoIncrementData;

diff --git a/src/main/java/s32x/sh2/Sh2Helper.java b/src/main/java/s32x/sh2/Sh2Helper.java
@@ -70,7 +70,7 @@ public Sh2Block addToKnownBlocks(Sh2Block b) {
             if (knownBlocks == Collections.EMPTY_MAP) {
                 knownBlocks = new HashMap<>(1);
             }
-            Sh2Block prev = knownBlocks.put(b.hashCodeWords & HASH_CODE_MASK, b);
+            Sh2Block prev = knownBlocks.putIfAbsent(b.hashCodeWords & HASH_CODE_MASK, b);
             //check for hash collisions
             assert prev != null ? prev == b : true;
             return prev;

diff --git a/src/main/java/s32x/sh2/cache/Sh2CacheImpl.java b/src/main/java/s32x/sh2/cache/Sh2CacheImpl.java
@@ -212,7 +212,7 @@ private int readCache(int addr, Size size) {
         int lruway = selectWayToReplace(cacheRegCtx.twoWay, ca.lru[entry]);
         assert cacheRegCtx.twoWay == 0 || (cacheRegCtx.twoWay == 1 && lruway > 1);
         final Sh2CacheLine line = ca.way[lruway][entry];
-        invalidatePrefetcher(line, entry, addr);
+        invalidatePrefetcher(line, entry, addr); //MetalHead needs this
         updateLru(lruway, ca.lru, entry);
         line.tag = tagaddr;
 

diff --git a/src/test/java/omegadrive/util/UtilTest.java b/src/test/java/omegadrive/util/UtilTest.java
@@ -65,6 +65,15 @@ public void testLongReadBoundary() {
         } //expected
     }
 
+    /**
+     * Chaotix 1994-12-07
+     * <p>
+     * 68k: LONG write to RAM 0xff_fffe, triggers an ArrayIndexOBE
+     * Hw is using two word writes: 0xFF_FFFE, and 0xFF_FFFE + 2 = 0x1_0000 = 0
+     * ie. the 2nd write goes to ROM area and it is ignored
+     * <p>
+     * works on hw
+     */
     @Test
     public void testLongWriteBoundary_NotSupported() {
         int address = 0xFEFFFE;