adjust enum name style

feilongjiang · Oct 26, 2023 · 593913e · 593913e
1 parent 069bb87
commit 593913e
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Showing 4 changed files with 24 additions and 24 deletions.
diff --git a/src/hotspot/cpu/riscv/assembler_riscv.hpp b/src/hotspot/cpu/riscv/assembler_riscv.hpp
@@ -1074,23 +1074,23 @@ enum operand_size { int8, int16, int32, uint32, int64 };
 
 #undef INSN
 
-enum FCLASS_MASK {
-  FCLASS_MINF       = 1 << 0,   // negative infinite
-  FCLASS_MNORM      = 1 << 1,   // negative normal number
-  FCLASS_MSUBNORM   = 1 << 2,   // negative subnormal number
-  FCLASS_MZERO      = 1 << 3,   // negative zero
-  FCLASS_PZERO      = 1 << 4,   // positive zero
-  FCLASS_PSUBNORM   = 1 << 5,   // positive subnormal number
-  FCLASS_PNORM      = 1 << 6,   // positive normal number
-  FCLASS_PINF       = 1 << 7,   // positive infinite
-  FCLASS_SNAN       = 1 << 8,   // signaling NaN
-  FCLASS_QNAN       = 1 << 9,   // quiet NaN
-  FCLASS_ZERO       = FCLASS_MZERO    | FCLASS_PZERO,
-  FCLASS_SUBNORM    = FCLASS_MSUBNORM | FCLASS_PSUBNORM,
-  FCLASS_NORM       = FCLASS_MNORM    | FCLASS_PNORM,
-  FCLASS_INF        = FCLASS_MINF     | FCLASS_PINF,
-  FCLASS_NAN        = FCLASS_SNAN     | FCLASS_QNAN,
-  FCLASS_FINITE     = FCLASS_ZERO     | FCLASS_SUBNORM   | FCLASS_NORM,
+enum {
+  fclass_minf       = 1 << 0,   // negative infinite
+  fclass_mnorm      = 1 << 1,   // negative normal number
+  fclass_msubnorm   = 1 << 2,   // negative subnormal number
+  fclass_mzero      = 1 << 3,   // negative zero
+  fclass_pzero      = 1 << 4,   // positive zero
+  fclass_psubnorm   = 1 << 5,   // positive subnormal number
+  fclass_pnorm      = 1 << 6,   // positive normal number
+  fclass_pinf       = 1 << 7,   // positive infinite
+  fclass_snan       = 1 << 8,   // signaling NaN
+  fclass_qnan       = 1 << 9,   // quiet NaN
+  fclass_zero       = fclass_mzero    | fclass_pzero,
+  fclass_subnorm    = fclass_msubnorm | fclass_psubnorm,
+  fclass_norm       = fclass_mnorm    | fclass_pnorm,
+  fclass_inf        = fclass_minf     | fclass_pinf,
+  fclass_nan        = fclass_snan     | fclass_qnan,
+  fclass_finite     = fclass_zero     | fclass_subnorm   | fclass_norm,
 };
 
 // Float and Double Conversion/Classify Instruction

diff --git a/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
@@ -1571,7 +1571,7 @@ void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRe
   is_double ? fclass_d(t1, src2)
             : fclass_s(t1, src2);
   orr(t0, t0, t1);
-  andi(t0, t0, Assembler::FCLASS_NAN); // if src1 or src2 is quiet or signaling NaN then return NaN
+  andi(t0, t0, Assembler::fclass_nan); // if src1 or src2 is quiet or signaling NaN then return NaN
   beqz(t0, Compare);
   is_double ? fadd_d(dst, src1, src2)
             : fadd_s(dst, src1, src2);
@@ -1670,7 +1670,7 @@ void C2_MacroAssembler::signum_fp(FloatRegister dst, FloatRegister src, FloatReg
             : fmv_s(dst, src);
 
   // check if input is -0, +0, signaling NaN or quiet NaN
-  andi(tmp1, tmp1, Assembler::FCLASS_ZERO | Assembler::FCLASS_NAN);
+  andi(tmp1, tmp1, Assembler::fclass_zero | Assembler::fclass_nan);
 
   bnez(tmp1, done);
 

diff --git a/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp b/src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
@@ -4228,7 +4228,7 @@ void MacroAssembler::FLOATCVT##_safe(Register dst, FloatRegister src, Register t
   fclass_##FLOATSIG(tmp, src);                                                            \
   mv(dst, zr);                                                                            \
   /* check if src is NaN */                                                               \
-  andi(tmp, tmp, Assembler::FCLASS_NAN);                                                  \
+  andi(tmp, tmp, Assembler::fclass_nan);                                                  \
   bnez(tmp, done);                                                                        \
   FLOATCVT(dst, src);                                                                     \
   bind(done);                                                                             \

diff --git a/src/hotspot/cpu/riscv/riscv.ad b/src/hotspot/cpu/riscv/riscv.ad
@@ -7292,7 +7292,7 @@ instruct isInfiniteF_reg_reg(iRegINoSp dst, fRegF src)
   format %{ "isInfinite $dst, $src" %}
   ins_encode %{
     __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
-    __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FCLASS_INF);
+    __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_inf);
     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
   %}
 
@@ -7307,7 +7307,7 @@ instruct isInfiniteD_reg_reg(iRegINoSp dst, fRegD src)
   format %{ "isInfinite $dst, $src" %}
   ins_encode %{
     __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
-    __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FCLASS_INF);
+    __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_inf);
     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
   %}
 
@@ -7322,7 +7322,7 @@ instruct isFiniteF_reg_reg(iRegINoSp dst, fRegF src)
   format %{ "isFinite $dst, $src" %}
   ins_encode %{
     __ fclass_s(as_Register($dst$$reg), as_FloatRegister($src$$reg));
-    __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FCLASS_FINITE);
+    __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_finite);
     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
   %}
 
@@ -7337,7 +7337,7 @@ instruct isFiniteD_reg_reg(iRegINoSp dst, fRegD src)
   format %{ "isFinite $dst, $src" %}
   ins_encode %{
     __ fclass_d(as_Register($dst$$reg), as_FloatRegister($src$$reg));
-    __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::FCLASS_FINITE);
+    __ andi(as_Register($dst$$reg), as_Register($dst$$reg), Assembler::fclass_finite);
     __ slt(as_Register($dst$$reg), zr, as_Register($dst$$reg));
   %}