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dependabot: Update golang dependencies #120

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Commits on May 16, 2023

  1. arc64: Add delay slot scheduler

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  2. arc64: Fix movmisalign patterns, and scale ld/st imms

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  3. Remove unused files

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  4. arc64: Remove 'Report'.

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  5. arc64: Update madd instructions to avoid dead code removal.

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  6. arc64: force to reg in vec_perm.

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  7. arc64: Add dot to matomic option description.

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  8. arc64: Update tests.

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  9. arc64: memcpy: update move ratio values.

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  10. arc64: Deal with 128b constants.

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  11. arc64: Change maximum number of bytes to allow 128 moves.

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  12. arc64: Remove duplicate macro

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  13. arc64: Mark blink alive when emitting a call to __tls_get_addr

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  14. arc64: Add PROFILE_HOOK

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  15. arc64: add macro to signal Hard-float ABI (#98) 

    This helps guard code in downstream projects such as glibc
related to hard-float regfile save/restore.

Granted we can do this with existing macros:
|
| #if defined(__ARCV3__) && defined (__ARC_HARD_FLOAT__)
|

keeping it independent of ISA keeps it future safe.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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  16. arc64: FP ABI update call used regs up to f15

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  17. arc64: Split 128b PIC addresses. 

    In rare cases we need to split 128b PIC access into two 64b
loads. Test provided.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  18. arc64: Add convertions from HF to DF and back

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  19. arc64: Fix mac constraints snafu.

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  20. arc64: Use swap with v2hi vectors.

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  21. arc64: Enable unaligned access for elf targets

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  22. arc64: Add MPYD(U), change MULT costs.

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  23. arc64: Fix dmpy int constraints

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  24. arc64: Add dmpywh instruction (used scalar)

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  25. arc64: Update accsi to accrn constraint

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  26. arc64: Improve and fix potential issues with 16b scalar ops

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  27. arc64: Update zero_ext cost, add new peephole pat

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  28. arc64: Update zero extend from hi.

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  29. arc64: Add sched info

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  30. arc64: Fix addressing local symb (large)

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  31. arc64: Use dedicated constraint for store type mems. 

    Also fix computing store/load instruction length.
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  32. arc64: Fix softfp move constraint letter snafu

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  33. arc64: Fix snafu when computing ld/st insns sizes.

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  34. arc64: Enable removable redundant extension instructions.

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  35. arc64/arcv2: fix triplet snafu

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  36. arc64: Add documentation.

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  37. arc64: Update constraints

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  38. arc64: Enforce the ld limm to be within 32bit range. 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  39. arc64: Widen the scope for base/index regs 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  40. arc64/arcv3: Check BE for TLS.

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  41. arc64: Don't use implicit dmacwh(u) output. 

    Any decision taken here will be probably for one benchmark not optimal
unless we can handle better the accumulator moves.  Until then don't
use accumulator as destination for dmacwhinsns.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  42. arc64: Add new mpyd/mac and mac/mac sched rules 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  43. arc64: Disable speculation when filling delay slots 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  44. arc64: TLS add a move before calling tls_get_addr

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  45. arc64: Use a conservative size estimation for branches when computing… 

    … loop body size.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  46. arc64: Introduce core register set 

    The Core Register Set are represented by r0-r31. Those registers are
the only ones which can be accessed by floating point conversion
instruction. Hence, introduce this register class to correctly
generate fp-conversion instructions.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  47. arc64: Introduce a fallback path when dbnz target is too far 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  48. [arc64] Add Exception handling builtins 

    Fixes a few failing cleanup tests.
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  49. [arc64/libgcc] Unwinding out of signal handler 

    This is mostly ported from ARCv2.  With this change the rest of
failing cleanup tests pass now.
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  50. arc64: Update dbnz's predicate and constraints 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  51. arc64: Update store c-letters for vector ops 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  52. arc64: Update FMA(s) instructions. Add Vector FP neg emulation

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  53. arc64: Fix dmpywh<u> instructions with immediate operands. 

    Introduce more predicates to filter out immediate operands when
dealing sign/zero extended instructions.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  54. arc64: remove faulty add/sub 16b pattern

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  55. arc64: Precompute TLS

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  56. arc64: Consolidate pushl/popl instructions

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  57. arc64: Add bswap32/64 ops

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  58. arc64: Keep close MAC-MOV instructions

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  59. arc64: Enable slow byte access for more efficient bitfield code.

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  60. arc64: Use 'int' as base for wchar_t

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  61. arc64: Add trap instruction

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  62. arc64: Emit aq.rl flags for new AMOs.

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  63. arc64: Use a PLUS operation while spliting the 64b imms as it generat… 

    …es more efficient code
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  64. arc64: Update rtx_costs factoring in mode size

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  65. arc64: Update add/sub with carry instructions

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  66. arc64: Add {add, sub, neg, mult} overflow patterns

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  67. arcXX: Fix overflow for mpy's

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  68. arc64: Add SETcc.f instruction.

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  69. arc64: Update alignments, add malloc alignment

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  70. Revert "arc64: Update alignments, add malloc alignment" 

    Errors reported

This reverts commit 9aa6c51.
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  71. [arc32] Initial commit

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  72. [arc32] iterate the call_insn

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  73. [arc32] iterate the sibcall_insn

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  74. [arc32] parameterise stack and parm boundaries

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  75. [arc32] pass "-mcpu=arc32" to gas

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  76. arc32: Update call templates for 32 bit

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  77. arc32: Disable 64bit instructions when 32bit

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  78. arcxx: Enable BI/BIH instructions by default

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  79. arc32: Changes to libgcc

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  80. arc32: Add CRT_CALL_STATIC 32b variant

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  81. arc32: Update MOVE_MAX and handling of const(...) printing

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  82. arc32: Use ti emulation only for arc64 builds

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  83. [arc32] Disable muldi3_highpart

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  84. [arc32] Add m32 flag to multilib

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  85. [arc32] Merge <optab> modes to cover DImode correctly

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  86. [arc32] Enable PC relative moves

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  87. arc32: Protect EPI iterator in 32b mode

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  88. [arc32] Trampoline generation handles 32 and 64 bits

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  89. arc32: Use "plt" iso "plt34" for addressing

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  90. arc64: Generalize split of double moves

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  91. arc32: Select the right emulation for 32b

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  92. arc32: Fix printing float numbers

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  93. arcv3: Use UNITS_PER_LIMM macro for FPU

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  94. arc32/dg.exp: Fix stack-usage-1

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  95. arc32: Add "-mll64" option

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  96. arc32: Disable "TARGET_LL64" when target isn't 32-bit

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  97. arc32: Introduce 64b double move splits

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  98. arc32: Update BIGGEST_ALIGNMENT.

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  99. arc32: Fix split double move

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  100. arcXX: Add mpyf test for flags update

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  101. arcXX: Consider the element of COMPLEX for reference pass check

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  102. arc32: Add -mcpu=hs{5,6}x option instead of -m{32,64} 

    -mcpu=hs6x is the default. Requires the latest patch in binutils
as well.
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  103. arc32: Add new ARCv3:32 triplet

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  104. arcXX: Fix warning.

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  105. arc64: Linux target is defaulting to 64bit arches

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  106. arc64: Cleanup rotate patterns

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  107. arc64: enable simple cc-reg mods

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  108. arc32: skip compile.exp=20000804-1.c

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  109. arc64: Don't use vadd2h as 16b scalar op

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  110. arc64: Update sched handling of acc regs. Add extra peephole step.

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  111. arc64: Add NAKED attribute

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  112. arc64: Add INTERRUPT attribute

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  113. arc64: Honor memory models for BL instructions.

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  114. arc64: Change modifier %h to %H, and %H to %V

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  115. arc64: Add BRcc support, peephole2 tier.

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  116. arc64: Update BRcc implementation.

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  117. arc64: Update rtx costs (16b)

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  118. arc32: Update LARGE memory model for HS5x

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  119. arc64: Update specific tests to work for HS5x

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  120. arc32: Honor large memory model for calls

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  121. arc64: Update predicated execution patterns. Disable BBITx gen.

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  122. arc64: Don't use pc-rel access for local symbols.

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  123. arc64: Update 64bit add/sub instructions, when 32b used, carry operat… 

    …ions are generated.
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  124. arc64: Fix mpy snafu

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  125. arc64: Enable unaligned access for linux toolchain

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  126. arc32: add lnx target triplet

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  127. arc32: add thread_pointer builtin

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  128. arc32: add tls offset

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  129. arc32: temporary fix for PIC symbols

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  130. arc32: fix libgcc config entry for hs5x

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  131. arc32: Update msimd option for HS5x CPUs

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  132. arc64: Don't allow const into mov operands

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  133. arc64: Update legitimate CONSTANT hook. Update movsi pattern.

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  134. arc64: Add zeroextend patterns for add[123],asl,asr, and lsr

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  135. arc64: Force any symbol out of the constant pool.

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  136. arc64: Don't allow symbols as constants when PIC

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  137. arc32: Allow 64b moves only when we have LL64

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  138. arc32: Update ldd/std mod letters.

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  139. arc32: Enable DBNZ for ARCv3/32

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  140. arcv3: update legitimate_address_1_p() to cover ldd

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  141. arcv3: adapt {restore,save}_callee_*() for ldd/std

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  142. arc64: Add zero-extend xbfu

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  143. arc32: Add "ldd/std" support 

    For calculating the costs, doing mem copies, prologue/epilogue generation.
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  144. arc32: Fix address scaling for double loads/stores 

    Plus the tests.
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  145. arcXX: Fix saving/restoring callee saved registers for double loads/s… 

    …tores
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  146. arc32: Enable 64b integer SIMD moves

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  147. arc64: Scalled offsets for double access addresses needs to be smalle… 

    …r than s9 field
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  148. arc32: Enable dot_prod4hi pattern.

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  149. arc64: Set schedule issue rate to 2

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  150. arc32:multilib: Update cpu list with hs68 and hs58

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  151. arc64: Update scaling tests

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  152. arc64: Fix double move spliting snafu

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  153. arc64: Update vect_perm cost.

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  154. arc32: Update v4hi vector reduction pattern

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  155. arc64: Make SIMD default for hs{5,6}8

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  156. ARC32: Fix vec wideining mult

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  157. arc64: Add vec_init pattern for v2si and v4hi vectors

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  158. arc64: Add predicated version for sign extend using ASR/ALR

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  159. arc64: Add accelerated vector reduction expands

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  160. arc64: Fix typo in {s,h,d}exch unspec names.

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  161. arc64: Support permutation vectors using vfexch insn. 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  162. arc64: Add support for VFUNPKL/VFUNPKM insns 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  163. arc64: Add vshuf tests for Float16 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  164. arc64: Add support for FVPACKL/FVPACKM 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  165. arc64: Add support for FVBFLYL/FVBFLYM 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  166. arc64: Cleanup arc64_simd_unpk func.

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  167. arc64: Add cadd90/cadd270 for FP vectors 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  168. arc64: Add cadd90/cadd270 for v2hi and v2si vectors 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  169. arc64: Fix predicate pattern for mulhisi 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  170. arc64: Add vpack2h shuffle patterns 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  171. arc32: Fix vec_pack_trunc snafu 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  172. arc64: Add v2hi init pattern. Not yet enabled 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  173. arc64: Add vmax2/vmin2 instructions. 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  174. arc64: Update vmax/vmin patterns

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  175. arc64: Update unspec patterns 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  176. arc64: Add combiner pattern for vpack2hl 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  177. arc64: Add more vpack4hl shuffle patterns 

    Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
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  178. arc64: Enable movcc and cbranchcc instructions

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  179. arc64: Add negcc and notcc patterns

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  180. arc64: fix negl snafu

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  181. arc64: Update notcc negcc patterns

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  182. arc64: Optimize cmov pattern

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  183. arc64: Update conditional mov patterns for FP modes

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  184. arc64: Add reloads for cnot/cneg

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  185. arc64: Cleanup md iterators

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  186. arc64: Add DWARF2 alternate CFA column.

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  187. arc64: Fix DWARF2 alternate CFA column patch 

    Use "REG_RET" instead of "ret".
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  188. arc64: Add an extra option to disable the vpack2h instructions.

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  189. arc64: Update mov.f pattern

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  190. arc64: Add fp-vector reverse shuffle

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  191. arc64: Add combiner pattern for vpack2wl

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  192. arc32: Add vect shifts for v2si

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  193. arcv3: Add the option to use FPRs for memory options 

    It is now possible to use floating point or vector registers to move
data.  This should reduce GPR pressure. A few examples would be:

128-bit vector: -mcpu=hs6x -m128  -mfpu=fpud -mwide -fpmov
 64-bit float:  -mcpu=hs6x        -mfpu=fpud        -fpmov

 Same support should be available for hs5x while using "-mll64"
 instead of "-m128". However, the compiler doesn't support such
 moves yet.  So it cannot be used in cpymem yet.
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  194. arc32: Adjust offset only when offset is positive

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  195. arc64: Add config support for --with-cpu=...

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  196. arc64: Update printing name of regs in ASM prologue

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  197. arc64: Update FP-ABI: all record types are passed via R-regs

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  198. arc64: Improve printing info about function frame

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  199. arc64: fix sanfu

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  200. arc64: unsigned max/min ops are synthesized using movcc, compare oper… 

    …ands can be two non-regs, fix it
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  201. arc64: Update compare test

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  202. arc64: Remove F16_ADD_IMM instructions

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  203. arc64: Chance fld128/fst128 to fldd64/fstd64

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  204. arc64: Guard remaining VPACK instructions

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  205. arc64: Update required by gcc12

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  206. arc64: Allow VPACK* insn with msimd opt

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  207. arc64: Update sth w6 instruction matching constraint

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  208. arc64: Add brgt,brhi,brle and brls instructions

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  209. arc64: Add support for 128b insteger vectors

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  210. arc64: Add 128b support for selected add, sub, max, min, mult and div… 

    … operations
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  211. arc64: Add split rule for (a & (1 << BIT_NO)) ? 0 : -1

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  212. arc64: Fix typo in reduc_plus_scal_v4si

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  213. Added / to the paths so the created folders dump1 and dump2 are corre… 

    …ctly accessed in the compilarion commands -dumpbase flag
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  214. ARC has no PIC register, so test 20020312-2.c should be skipped

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  215. [ARC32] Check if assembler can do TLS 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  216. [arc64] Add bclr pattern 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  217. [arc64] Update dbnz pattern 

    DBNZ pattern can clobber the CC register. Add this information to dbnz pattern.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  218. [MAINLINE] Fix loop's data flow computation 

    *NOT FINAL SOLUTION*
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  219. arc64: Update contraints for btst instructions

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  220. [MAINLINE] Dataflow: Update df_analyze_loop to take into account the … 

    …exit edges.

Problem statement:

The doloop_end pattern can sometimes overwrite registers that are
still in use at the end of a loop. This problem is addressed by the
doloop_optimize function, which examines the data flow information for
the blocks within a loop using df_analyze_loop(). However, the
df_analyze_loop() doesn't do the data flow analyzis for the blocks to where
the loop exits. As a result, the doloop_optimize function is unable to
determine whether the doloop_end pattern sequence will overwrite a
register that is still needed at the end of the block.

Example:

  +----------------------------------------------+
  |                                              |
  |                         | [e1]               |
  |                         v                    |
  |                       +---------------+      | [e4]
  |                       | BASIC_BLOCK 2 |      |
  |                       +---------------+      |
  |                         |                    |
  |                         | [e2]               |
  |                         v                    |
+---------------+  [e3]   +---------------+      |
| BASIC_BLOCK 6 | <------ | BASIC_BLOCK 3 | <----+
+---------------+         +---------------+
			    |
			    | [e5: CC live]
			    v
			  +---------------+
		    <-----| BASIC_BLOCK 4 |
		          +---------------+
                            |
                            v

We have a loop that is made of basic blocks 3 and 6. The loop exits
via edge [e5] to basic block 4. The CC-register is set in basic block
3, and used by the conditional jump instruction of basic block 3, and
conditional jump instruction of basic block 4. Thus, the CC-regiter
(flags) is live over the edge [e5]. Example attached.

Using the unpatched df_analyze_loop() routine, the CC-register is not
find alive on the loop's exit edge, which may lead to errors.

Solution:

The proposed solution is to take into account the basic blocks to
which a loop may exit in the partial data flow analysis, namely,
changing the loop_post_order_compute() and
loop_inverted_post_order_compute() routines.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  221. arc64: Enable TARGET_ARRAY_MODE_SUPPORTED_P hook 

    Improve the use of vector/double loads optimizations for scalar access.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  222. arc64: Wide FSIMD and int SIMD are on by default. 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  223. arc64: Update complex add patterns 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  224. arc64: Don't use .di flag for ldl/stl instructions 

    Throw an warning when -Waddress is used

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  225. arc64: Fix compilation warnings 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  226. arc: Make TLS Local Dynamic work like Global Dynamic model 

    The Local Dynamic model is better handled by using more generic Global
Dynamic model and accesses using anchors.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  227. arc64: Enable extra vector tests 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  228. arc64: Use bclrl,bsetl and vpack to load large integers

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  229. arc64: Update target-supports to enable atomic tests.

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  230. arc64: Fix dg predicate for ARC64/ARC32 toolchain

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  231. arc64: Remove dbxelf.h reference 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  232. arc64: Remove @gol cmd from documentation 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  233. arc64: Update TARGET_VECTORIZE_VEC_PERM_CONST 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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  234. arc64: Update unwinding hooks 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Commits on May 17, 2023

  1. arc64: Support for C2x varargs 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Commits on Jun 23, 2023

  1. arc64: Introduce vector 4hi duplicate for ARC32 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Commits on Jul 17, 2023

  1. ARC32: Add support for PUSH_S/POP_S

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Commits on Jul 18, 2023

  1. ARC32: Update tests to recognize PUSH/POP

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Commits on Aug 1, 2023

  1. arc64: Add TLS LE alignment test. 

    Check if the linker resolves correctly the R_ARC_TLS_LE_32 relocation.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Commits on Aug 18, 2023

  1. arc64: implement {push,pop}dl_s instructions 

    This commit adds 128-bit forms of push and pop using the movTI_insn
pattern and an implicit stack pointer operand. For the needs of these
instructions, the Ustk constraints are relaxed to accept TImode
operands.

Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
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  2. gcc/testsuite: adjust interrupt-5.c for 128-bit push/pop 

    In the arc64-specific test with 128-bit loads/stores, replace the
lddl/stdl instructions involving the stack pointer to their
pushdl_s/popdl_s counterparts.

Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
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Commits on Sep 18, 2023

  1. Update GCC Driver Configuration for ARCv2 Toolchain Compatibility 

    Configured GCC driver to set GNU AS and GNU LD as default
assembler and linker for ARCv2

Signed-off-by: Luis Silva <luis.m.silva99@hotmail.com>
    @luismgsilva @claziss
    luismgsilva authored and claziss committed Sep 18, 2023
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  2. Update GCC Driver Configuration for ARCv3 Toolchain Compatibility 

    Configured GCC driver to set GNU AS and GNU LD as default
assembler and linker for ARCv3

Signed-off-by: Luis Silva <luis.m.silva99@hotmail.com>
    @luismgsilva @claziss
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Commits on Sep 19, 2023

  1. arc64: Enable IPA-RA 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Commits on Oct 5, 2023

  1. arc64: Use 128bit ops for moving data 

    This is done by preferring the V8HI and V4SI modes whenever m128 is available

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Commits on Dec 6, 2023

  1. arc64: Remove faulty sub.f pattern. 

    Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Commits on Jan 9, 2024

  1. arc64: Update mpyd and macd instructions 

    When operating in 32bit CPUs use reg-pairs

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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    claziss committed Jan 9, 2024
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Commits on Feb 28, 2024

  1. [arc64] Fix removing active instruction 

    In MACH, we try to correct superflu movest from accumulator to a GPR
by indentifying the MAC instruction and the superflu move, and
combining those two into a single MAX instruction having the GPR as a
destination.
In the original algorithm, I was asking for next real instruction
which is can retrive an instruction acoss BB boundary which is not
correct. Thus, this patch.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
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Commits on Mar 19, 2024

  1. arc64: Saner acceptance of immediates by arc64_legitimate_address_p() 

    Before this change, cc1(plus) could emit "store" insturctions such as:

stl 0x1234, [0x80_0000_1000]

which would become "stl 0x1234, [0x1000]" by the "as"sembler.

This happened, because "arc64_legitimate_address_1_p()" was returning
"true" for any sort of "const_int"s.  With this change, it returns
"true" only if the number can fit in 32-bit, and "false" otherwise.

The address preparation as performed by "arc64_prepare_move_operands()"
during the "movdi expand" has already taken care of the rest:

(define_predicate "splittable_const_int_operand"
  (match_code "const_int")
{
  ...
  /* Check if the constant can be loaded in a single bsetl/bclrl insn. */
  if ((SINGLE_BIT_MASK_OPERAND (zext_hwi (INTVAL (op) >> 32, 32))
       && UNSIGNED_INT32 (zext_hwi (INTVAL (op), 32)))
      || (SINGLE_BIT_MASK_OPERAND (zext_hwi ((~INTVAL (op)) >> 32, 32))
          && (sext_hwi (INTVAL (op), 32) < 0)))
    return false;
  ...
}

Because of this logic, there's no need for a split and a mere
"bsetl r0, 0x1000, 39" will get the job done.
    Shahab Vahedi committed Mar 19, 2024
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Commits on Jun 4, 2024

  1. dependabot: Update golang dependencies 

    This commit fixies the following security vulnerabilities:
- HTTP/2 rapid reset can cause excessive work in net/http;
- golang.org/x/net/http2 vulnerable to possible excessive memory growth;
- net/http, x/net/http2: close connections when receiving too many headers;
- Prefix Truncation Attack against ChaCha20-Poly1305 and Encrypt-then-MAC aka Terrapin;
- HTTP/2 Stream Cancellation Attack;
- Improper rendering of text nodes in golang.org/x/net/html.

Signed-off-by: Evgeny Semenov <semenov@synopsys.com>
    @qwersem
    qwersem committed Jun 4, 2024
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