vdebug/xtensa: LX8 palladium support

- LX8 Palladium example config
- Dual NX Palladium example config
- Fix for VDebug socket creation on Cygwin

Signed-off-by: ianst <ianst@cadence.com>

src/jtag/drivers/vdebug.c

@@ -253,6 +253,11 @@ static int vdebug_socket_open(char *server_addr, uint32_t port)
 	hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP);
 	if (hsock == INVALID_SOCKET)
 		rc = vdebug_socket_error();
+#elif defined __CYGWIN__
+	/* SO_RCVLOWAT unsupported */
+	hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP);
+	if (hsock < 0)
+		rc = errno;
 #else
 	uint32_t rcvwat = VD_SHEADER_LEN;    /* size of the rcv header, as rcv min watermark */
 	hsock = socket(AF_INET, SOCK_STREAM, IPPROTO_IP);

tcl/board/xtensa-palladium-vdebug-dual.cfg

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+source [find interface/vdebug.cfg]
+
+# vdebug select JTAG transport
+transport select jtag
+
+# JTAG reset config, frequency and reset delay
+reset_config trst_and_srst
+adapter speed 50000
+adapter srst delay 5
+
+source [find target/vd_xtensa_jtag_dual.cfg]

tcl/target/vd_xtensa_jtag.cfg

@@ -0,0 +1,32 @@
+# Copyright (C) 2020-2021 Cadence Design Systems, Inc.
+# Ian Thompson <ianst@cadence.com>
+#
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+# TODO: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+#vdebug bfm_path dut_top.JTAG 10ns
+vdebug bfm_path Testbench.VJTAG 10ns
+
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Create Xtensa target first
+source [find target/xtensa.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config" 
+
+# register target
+proc vdebug_examine_end {} {
+#    vdebug register_target
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { vdebug_examine_end }
+

tcl/target/vd_xtensa_jtag_dual.cfg

@@ -0,0 +1,33 @@
+# Copyright (C) 2020-2021 Cadence Design Systems, Inc.
+# Ian Thompson <ianst@cadence.com>
+#
+# Cadence virtual debug interface
+# for Palladium emulation systems
+#
+
+# TODO: Enable backdoor memory access
+# set _MEMSTART 0x00000000
+# set _MEMSIZE 0x100000
+
+# BFM hierarchical path and input clk period
+#vdebug bfm_path dut_top.JTAG 10ns
+vdebug bfm_path Testbench.VJTAG 10ns
+
+# DMA Memories to access backdoor (up to 4)
+# vdebug mem_path tbench.u_mcu.u_sys.u_itcm_ram.Mem $_MEMSTART $_MEMSIZE
+
+# Create Xtensa target first
+source [find target/xtensa_dual.cfg]
+
+# Configure Xtensa core parameters next
+# Generate [xtensa-core-XXX.cfg] via "xt-gdb --dump-oocd-config" 
+
+# register target
+proc vdebug_examine_end {} {
+#    vdebug register_target
+}
+
+# Default hooks
+$_TAPNAME0 configure -event examine-end { vdebug_examine_end }
+$_TAPNAME1 configure -event examine-end { vdebug_examine_end }
+