Skip to content
forked from Xilinx/ACCL

Accelerated Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

License

Notifications You must be signed in to change notification settings

fpgasystems/ACCL

 
 

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

ACCL: Accelerated Collective Communication Library

* Note: This project is under active development. We will tag a stable release soon.*

ACCL is a Vitis kernel and associated XRT drivers which together provide MPI-like collectives for Xilinx FPGAs. ACCL is designed to enable compute kernels resident in FPGA fabric to communicate directly under host supervision but without requiring data movement between the FPGA and host. Instead, ACCL uses Vitis-compatible TCP and UDP stacks to connect FPGAs directly over Ethernet at up to 100 Gbps on Alveo cards.

ACCL currently supports Send/Recv and the following collectives:

  • Broadcast
  • Scatter
  • Gather
  • All-gather
  • Reduce
  • All-reduce
  • Reduce-Scatter

Installation

See INSTALL.md to learn how to build ACCL-enabled designs and interact with them from C++. To use ACCL from Python, refer to PyACCL.

Citation

If you use our work or would like to cite it in your own, please use the following citation:

@INPROCEEDINGS{9651265,
  author={He, Zhenhao and Parravicini, Daniele and Petrica, Lucian and O’Brien, Kenneth and Alonso, Gustavo and Blott, Michaela},
  booktitle={2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)},
  title={ACCL: FPGA-Accelerated Collectives over 100 Gbps TCP-IP},
  year={2021},
  volume={},
  number={},
  pages={33-43},
  doi={10.1109/H2RC54759.2021.00009}}

About

Accelerated Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators

Resources

License

Stars

Watchers

Forks

Packages

No packages published

Languages

  • C++ 57.7%
  • Tcl 21.4%
  • C 10.8%
  • Verilog 3.3%
  • Makefile 3.2%
  • Python 1.8%
  • Other 1.8%