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DTL H2000 hardware reverse engineering

Nicolas Noble edited this page Feb 27, 2020 · 20 revisions

100 pins bridge

On the DTL-H2000, the SBUS of the PlayStation has several buffers and level translators, unlike the retail hardware. Tracing through it is therefore a bit more difficult.

The most important piece of information however is probably the pinout of the 100 pins bridge over the two cards. It contains all of the SBUS signals, and more. Note that most of these signals won't go directly to their respective devices, but instead will go over level translators and buffers. The buffers will usually force the signal direction in a certain way only, and this will be described when applicable in the table below.

signal CPU tr pin translator br tr pin br pin br tr pin translator PIO tr pin
GND 1
GND 2
3
4
5
A23(?) 6
A22(?) 7
A21(?) 8
A20(?) 9
GND 10
A19(?) 11
A18(?) 12
A17 13
A16 14
GND 15
A15 16
A14 17
A13 18
A12 19
GND 20
A11 21
A10 22
A9 23
A8 24
GND 25
A7(?) 26
A6 27
A5 28
A4 29
GND 30
A3 31
A2 32
A1 33
A0 34 U65 13
35
D15 36 47 (1A1) U732 2 (1B1)
D14 37 46 (1A2) U732 3 (1B2)
D13 38 44 (1A3) U732 5 (1B3)
D12 39 43 (1A4) U732 6 (1B4)
GND 40
D11 41 41 (1A5) U732 8 (1B5)
D10 42 40 (1A6) U732 9 (1B6)
D9 43 38 (1A7) U732 11 (1B7)
D8 44 37 (1A8) U732 12 (1B8)
GND 45
D7 46 36 (2A1) U732 13 (2B1)
D6 47 35 (2A2) U732 14 (2B2)
D5 48 33 (2A3) U732 16 (2B3)
D4 49 32 (2A4) U732 17 (2B4)
GND 50
D3 51 30 (2A5) U732 19 (2B5)
D2 52 29 (2A6) U732 20 (2B6)
D1 53 27 (2A7) U732 22 (2B7)
D0 54 26 (2A8) U732 23 (2B8)
47 U64 2
GND 55
56
57
58
GND 59
60
61
62
63
64
65
66
!RESET 11 (2Y3) U65 38 (2A3) <--67-- 8 (2Y1) U737 41 (2A1)
68
GND 69
70
71
72
73
74
75
76
77
GND 78
79
GND 80
81
82
83
GND 84
85
86
87
GND 88
89
GND 90
91
92
93
94
95
96
97
98
GND 99
GND 100