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update dramsim3.h
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SeonjinNa committed Sep 22, 2023
1 parent 9e4a331 commit bdda1ae
Showing 1 changed file with 5 additions and 9 deletions.
14 changes: 5 additions & 9 deletions src/dram_dramsim3.h
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ POSSIBILITY OF SUCH DAMAGE.

/**********************************************************************************************
* File : dram_dramsim3.h
* Author : HPArch Research Group(Seonjin Na)
* Author : HPArch Research Group (Seonjin Na)
* Date : 9/21/2023
* Description : DRAMSim3 interface
*********************************************************************************************/
Expand All @@ -48,7 +48,7 @@ class JedecDRAMSystem;
};

///////////////////////////////////////////////////////////////////////////////////////////////
/// \brief MC - DRAMSim2 interface
/// \brief MC - DRAMSim3 interface
///////////////////////////////////////////////////////////////////////////////////////////////
class dram_dramsim3_c : public dram_c
{
Expand Down Expand Up @@ -78,10 +78,6 @@ class dram_dramsim3_c : public dram_c
*/
void run_a_cycle(bool);

void read_callback2(uint64_t);

void write_callback2(uint64_t);

private:
dram_dramsim3_c(); // do not implement

Expand All @@ -95,9 +91,9 @@ class dram_dramsim3_c : public dram_c
*/
void write_callback(unsigned, uint64_t, uint64_t);

// void read_callback2(uint64_t);
void read_callback2(uint64_t);

// void write_callback2(uint64_t);
void write_callback2(uint64_t);

/**
* Send a packet to NOC
Expand All @@ -113,7 +109,7 @@ class dram_dramsim3_c : public dram_c
list<mem_req_s*>* m_output_buffer; /**< output buffer */
list<mem_req_s*>* m_tmp_output_buffer; /**< output buffer */
list<mem_req_s*>* m_pending_request; /**< pending request */
dramsim3::Config *m_config;
// dramsim3::Config *m_config;
dramsim3::JedecDRAMSystem *m_dramsim; /**< dramsim3 instance */
};
#endif
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