updated port spec (#471)

gussmith23 · Sep 19, 2024 · 44522d8 · 44522d8
1 parent f8ae396
commit 44522d8
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/integration_tests/lakeroad/bsg_mul_add_unsigned/bsg_mul_add_unsigned_13bit.sv b/integration_tests/lakeroad/bsg_mul_add_unsigned/bsg_mul_add_unsigned_13bit.sv
@@ -10,9 +10,9 @@
 // RUN: --pipeline-depth 0 \
 // RUN: --clock-name clk_i \
 // RUN: --module-name test_module \
-// RUN: --input-signal a_i:13 \
-// RUN: --input-signal b_i:13 \
-// RUN: --input-signal c_i:26 \
+// RUN: --input-signal 'a:(port a_i 13):13' \
+// RUN: --input-signal 'b:(port b_i 13):13' \
+// RUN: --input-signal 'c:(port c_i 26):26' \
 // RUN: --timeout 270 \
 // RUN: > $outfile
 // RUN: cat $outfile