v4.13.0 (#6)

Co-authored-by: HailoRT-Automation <contact@hailo.ai>

.gitignore

@@ -0,0 +1,13 @@
+.Module.symvers.cmd
+Module.symvers
+.modules.order.cmd
+modules.order
+*.mod.c
+*.o
+*.o.cmd
+*.ko
+*.ko.cmd
+*.mod
+*.mod.cmd
+
+linux/pcie/build

README.md

@@ -5,9 +5,8 @@
 
 # Hailo PCIe driver #
 
-Hailo's PCIe driver is required when working with a Hailo device via the PCIe interface. It links the [**HailoRT library**](https://github.com/hailo-ai/hailort)
-and the device, and loads the device's firmware when working through this interface. The device driver
-is used to manage the Hailo device, communicate with the device and transfer data to/from the device.
+The Hailo PCIe driver is necessary for interacting with a Hailo device over the PCIe interface. It connects the [**HailoRT library**](https://github.com/hailo-ai/hailort) to the device and loads the
+device's firmware when using this interface. The driver is responsible for managing the Hailo device, communicating with it, and transferring data to and from the device.
 
 ## Usage and Compilation
 

common/fw_validation.c

@@ -36,8 +36,8 @@ int FW_VALIDATION__validate_fw_header(uintptr_t firmware_base_address,
     case HAILO_BOARD_TYPE_HAILO8:
         expected_firmware_magic = FIRMWARE_HEADER_MAGIC_HAILO8; 
         break;
-    case HAILO_BOARD_TYPE_MERCURY:
-        expected_firmware_magic = FIRMWARE_HEADER_MAGIC_MERCURY; 
+    case HAILO_BOARD_TYPE_HAILO15:
+        expected_firmware_magic = FIRMWARE_HEADER_MAGIC_HAILO15; 
         break;
     default:
         err = -EINVAL;

common/fw_validation.h

@@ -10,7 +10,7 @@
 #include "hailo_ioctl_common.h"
 
 #define FIRMWARE_HEADER_MAGIC_HAILO8 (0x1DD89DE0)
-#define FIRMWARE_HEADER_MAGIC_MERCURY (0xE905DAAB)
+#define FIRMWARE_HEADER_MAGIC_HAILO15 (0xE905DAAB)
 
 #ifndef HAILO_EMULATOR
 #define FIRMWARE_WAIT_TIMEOUT_MS (5000)

common/hailo_ioctl_common.h

@@ -7,8 +7,6 @@
 #define _HAILO_IOCTL_COMMON_H_
 
 
-#define DESCRIPTORS_IN_BUFFER(buffer_size, desc_page_size) (((buffer_size) + (desc_page_size) - 1) / (desc_page_size))
-
 // This value is not easily changeable.
 // For example: the channel interrupts ioctls assume we have up to 32 channels
 #define MAX_VDMA_CHANNELS_PER_ENGINE    (32)
@@ -19,7 +17,6 @@
 #define CHANNEL_IRQ_TIMESTAMPS_SIZE (128 * 2) // Should be same as MAX_IRQ_TIMESTAMPS_SIZE (hailort_driver.hpp)
 #define CHANNEL_IRQ_TIMESTAMPS_SIZE_MASK (CHANNEL_IRQ_TIMESTAMPS_SIZE - 1)
 
-#define INVALID_CHANNEL_HANDLE_VALUE    ((uint64_t)-1)
 #define INVALID_DRIVER_HANDLE_VALUE     ((uintptr_t)-1)
 
 // Used by windows and unix driver to raise the right CPU control handle to the FW. The same as in pcie_service FW 
@@ -153,54 +150,43 @@ struct hailo_desc_list_bind_vdma_buffer_params {
     uintptr_t desc_handle;      // in
     uint16_t desc_page_size;    // in
     uint8_t channel_index;      // in
-    size_t offset;              // in
+    uint32_t starting_desc;     // in
 };
 
-/* structure used in ioctl HAILO_VDMA_CHANNEL_ENABLE */
-struct hailo_vdma_channel_enable_params {
-    uint8_t engine_index;                       // in
-    uint8_t channel_index;                      // in
-    enum hailo_dma_data_direction direction;    // in
-    bool enable_timestamps_measure;             // in
-    uint64_t channel_handle;                    // out
+/* structure used in ioctl HAILO_VDMA_INTERRUPTS_ENABLE */
+struct hailo_vdma_interrupts_enable_params {
+    uint32_t channels_bitmap_per_engine[MAX_VDMA_ENGINES];  // in
+    bool enable_timestamps_measure;                         // in
 };
 
-/* structure used in ioctl HAILO_VDMA_CHANNEL_DISABLE */
-struct hailo_vdma_channel_disable_params {
-    uint8_t engine_index;    // in
-    uint8_t channel_index;   // in
-    uint64_t channel_handle; // in
+/* structure used in ioctl HAILO_VDMA_INTERRUPTS_DISABLE */
+struct hailo_vdma_interrupts_disable_params {
+    uint32_t channels_bitmap_per_engine[MAX_VDMA_ENGINES];  // in
 };
 
-/* structure used in ioctl HAILO_VDMA_CHANNEL_WAIT_INT */
-struct hailo_vdma_channel_wait_params {
-    uint8_t engine_index;                                                               // in
-    uint8_t channel_index;                                                              // in
-    uint64_t channel_handle;                                                            // in
-    uint64_t timeout_ms;                                                                // in
-    uint32_t timestamps_count;                                                          // inout
-// In linux send address to local buffer because there isnt room on stack for array
-#if defined(__linux__)
-    struct hailo_channel_interrupt_timestamp *timestamps;                               // out
-#elif defined(__QNX__) || defined(_MSC_VER)
-    struct hailo_channel_interrupt_timestamp timestamps[CHANNEL_IRQ_TIMESTAMPS_SIZE];   // out
-#else
-#error "unsupported platform!"
-#endif // __linux__  
+/* structure used in ioctl HAILO_VDMA_INTERRUPTS_WAIT */
+struct hailo_vdma_interrupts_channel_data {
+    uint8_t engine_index;
+    uint8_t channel_index;
+    bool is_active;                 // If not activate, num_processed is ignored.
+    uint16_t host_num_processed;
+    uint8_t host_error;             // Channel errors bits on source side
+    uint8_t device_error;           // Channel errors bits on dest side
 };
 
-/* structure used in ioctl HAILO_VDMA_CHANNEL_ABORT */
-struct hailo_vdma_channel_abort_params {
-    uint8_t engine_index;       // in
-    uint8_t channel_index;      // in
-    uint64_t channel_handle;    // in
+struct hailo_vdma_interrupts_wait_params {
+    uint32_t channels_bitmap_per_engine[MAX_VDMA_ENGINES];          // in
+    uint8_t channels_count;                                         // out
+    struct hailo_vdma_interrupts_channel_data
+        irq_data[MAX_VDMA_CHANNELS_PER_ENGINE * MAX_VDMA_ENGINES];  // out
 };
 
-/* structure used in ioctl HAILO_VDMA_CHANNEL_CLEAR_ABORT */
-struct hailo_vdma_channel_clear_abort_params {
-    uint8_t engine_index;       // in
-    uint8_t channel_index;      // in
-    uint64_t channel_handle;    // in
+/* structure used in ioctl HAILO_VDMA_INTERRUPTS_READ_TIMESTAMPS */
+struct hailo_vdma_interrupts_read_timestamp_params {
+    uint8_t engine_index;                                                               // in
+    uint8_t channel_index;                                                              // in
+    uint32_t timestamps_count;                                                          // out
+    struct hailo_channel_interrupt_timestamp timestamps[CHANNEL_IRQ_TIMESTAMPS_SIZE];   // out
 };
 
 /* structure used in ioctl HAILO_FW_CONTROL */
@@ -299,10 +285,10 @@ enum hailo_vdma_buffer_sync_type {
 };
 
 struct hailo_vdma_buffer_sync_params {
-    size_t handle;                                      // in
-    enum hailo_vdma_buffer_sync_type  sync_type;        // in
-    void*                             buffer_address;   // in
-    uint64_t                          buffer_size;      // in
+    size_t handle;                              // in
+    enum hailo_vdma_buffer_sync_type sync_type; // in
+    size_t offset;                              // in
+    size_t count;                               // in
 };
 
 /* structure used in ioctl HAILO_READ_NOTIFICATION */
@@ -315,7 +301,7 @@ struct hailo_d2h_notification {
 
 enum hailo_board_type {
     HAILO_BOARD_TYPE_HAILO8 = 0,
-    HAILO_BOARD_TYPE_MERCURY,
+    HAILO_BOARD_TYPE_HAILO15,
     HAILO_BOARD_TYPE_COUNT,
 
     /** Max enum value to maintain ABI Integrity */
@@ -399,11 +385,10 @@ enum hailo_general_ioctl_code {
 #define HAILO_RESET_NN_CORE             _IO_(HAILO_GENERAL_IOCTL_MAGIC,    HAILO_RESET_NN_CORE_CODE)
 
 enum hailo_vdma_ioctl_code {
-    HAILO_VDMA_CHANNEL_ENABLE_CODE,
-    HAILO_VDMA_CHANNEL_DISABLE_CODE,
-    HAILO_VDMA_CHANNEL_WAIT_INT_CODE,
-    HAILO_VDMA_CHANNEL_ABORT_CODE,
-    HAILO_VDMA_CHANNEL_CLEAR_ABORT_CODE,
+    HAILO_VDMA_INTERRUPTS_ENABLE_CODE,
+    HAILO_VDMA_INTERRUPTS_DISABLE_CODE,
+    HAILO_VDMA_INTERRUPTS_WAIT_CODE,
+    HAILO_VDMA_INTERRUPTS_READ_TIMESTAMPS_CODE,
     HAILO_VDMA_CHANNEL_READ_REGISTER_CODE,
     HAILO_VDMA_CHANNEL_WRITE_REGISTER_CODE,
     HAILO_VDMA_BUFFER_MAP_CODE,
@@ -422,29 +407,29 @@ enum hailo_vdma_ioctl_code {
     HAILO_VDMA_IOCTL_MAX_NR,
 };
 
-#define HAILO_VDMA_CHANNEL_ENABLE           _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_ENABLE_CODE,         struct hailo_vdma_channel_enable_params)
-#define HAILO_VDMA_CHANNEL_DISABLE          _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_DISABLE_CODE,        struct hailo_vdma_channel_disable_params)
-#define HAILO_VDMA_CHANNEL_WAIT_INT         _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_WAIT_INT_CODE,       struct hailo_vdma_channel_wait_params)
-#define HAILO_VDMA_CHANNEL_ABORT            _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_ABORT_CODE,          struct hailo_vdma_channel_abort_params)
-#define HAILO_VDMA_CHANNEL_CLEAR_ABORT      _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_CLEAR_ABORT_CODE,    struct hailo_vdma_channel_clear_abort_params)
-#define HAILO_VDMA_CHANNEL_READ_REGISTER    _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_READ_REGISTER_CODE,  struct hailo_vdma_channel_read_register_params)
-#define HAILO_VDMA_CHANNEL_WRITE_REGISTER   _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_WRITE_REGISTER_CODE, struct hailo_vdma_channel_write_register_params)
+#define HAILO_VDMA_INTERRUPTS_ENABLE          _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_INTERRUPTS_ENABLE_CODE,            struct hailo_vdma_interrupts_enable_params)
+#define HAILO_VDMA_INTERRUPTS_DISABLE         _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_INTERRUPTS_DISABLE_CODE,           struct hailo_vdma_interrupts_disable_params)
+#define HAILO_VDMA_INTERRUPTS_WAIT            _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_INTERRUPTS_WAIT_CODE,              struct hailo_vdma_interrupts_wait_params)
+#define HAILO_VDMA_INTERRUPTS_READ_TIMESTAMPS _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_INTERRUPTS_READ_TIMESTAMPS_CODE,   struct hailo_vdma_interrupts_read_timestamp_params)
+
+#define HAILO_VDMA_CHANNEL_READ_REGISTER      _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CHANNEL_READ_REGISTER_CODE,         struct hailo_vdma_channel_read_register_params)
+#define HAILO_VDMA_CHANNEL_WRITE_REGISTER     _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_CHANNEL_WRITE_REGISTER_CODE,        struct hailo_vdma_channel_write_register_params)
 
-#define HAILO_VDMA_BUFFER_MAP               _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_BUFFER_MAP_CODE,            struct hailo_vdma_buffer_map_params)
-#define HAILO_VDMA_BUFFER_UNMAP             _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_BUFFER_UNMAP_CODE,          struct hailo_vdma_buffer_unmap_params)
-#define HAILO_VDMA_BUFFER_SYNC              _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_BUFFER_SYNC_CODE,           struct hailo_vdma_buffer_sync_params)
+#define HAILO_VDMA_BUFFER_MAP                 _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_BUFFER_MAP_CODE,                    struct hailo_vdma_buffer_map_params)
+#define HAILO_VDMA_BUFFER_UNMAP               _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_BUFFER_UNMAP_CODE,                  struct hailo_vdma_buffer_unmap_params)
+#define HAILO_VDMA_BUFFER_SYNC                _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_VDMA_BUFFER_SYNC_CODE,                   struct hailo_vdma_buffer_sync_params)
 
-#define HAILO_DESC_LIST_CREATE              _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_DESC_LIST_CREATE_CODE,           struct hailo_desc_list_create_params)
-#define HAILO_DESC_LIST_RELEASE             _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_DESC_LIST_RELEASE_CODE,          uintptr_t)
-#define HAILO_DESC_LIST_BIND_VDMA_BUFFER    _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_DESC_LIST_BIND_VDMA_BUFFER_CODE, struct hailo_desc_list_bind_vdma_buffer_params)
+#define HAILO_DESC_LIST_CREATE                _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_DESC_LIST_CREATE_CODE,                   struct hailo_desc_list_create_params)
+#define HAILO_DESC_LIST_RELEASE               _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_DESC_LIST_RELEASE_CODE,                  uintptr_t)
+#define HAILO_DESC_LIST_BIND_VDMA_BUFFER      _IOR_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_DESC_LIST_BIND_VDMA_BUFFER_CODE,         struct hailo_desc_list_bind_vdma_buffer_params)
 
-#define HAILO_VDMA_LOW_MEMORY_BUFFER_ALLOC  _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_LOW_MEMORY_BUFFER_ALLOC_CODE, struct hailo_allocate_low_memory_buffer_params)
-#define HAILO_VDMA_LOW_MEMORY_BUFFER_FREE   _IO_(HAILO_VDMA_IOCTL_MAGIC,   HAILO_VDMA_LOW_MEMORY_BUFFER_FREE_CODE)
+#define HAILO_VDMA_LOW_MEMORY_BUFFER_ALLOC    _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_LOW_MEMORY_BUFFER_ALLOC_CODE,       struct hailo_allocate_low_memory_buffer_params)
+#define HAILO_VDMA_LOW_MEMORY_BUFFER_FREE     _IO_(HAILO_VDMA_IOCTL_MAGIC,   HAILO_VDMA_LOW_MEMORY_BUFFER_FREE_CODE)
 
-#define HAILO_MARK_AS_IN_USE                _IOW_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_MARK_AS_IN_USE_CODE,             struct hailo_mark_as_in_use_params)
+#define HAILO_MARK_AS_IN_USE                  _IOW_(HAILO_VDMA_IOCTL_MAGIC,  HAILO_MARK_AS_IN_USE_CODE,                     struct hailo_mark_as_in_use_params)
 
-#define HAILO_VDMA_CONTINUOUS_BUFFER_ALLOC  _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CONTINUOUS_BUFFER_ALLOC_CODE, struct hailo_allocate_continuous_buffer_params)
-#define HAILO_VDMA_CONTINUOUS_BUFFER_FREE   _IO_(HAILO_VDMA_IOCTL_MAGIC,   HAILO_VDMA_CONTINUOUS_BUFFER_FREE_CODE)
+#define HAILO_VDMA_CONTINUOUS_BUFFER_ALLOC    _IOWR_(HAILO_VDMA_IOCTL_MAGIC, HAILO_VDMA_CONTINUOUS_BUFFER_ALLOC_CODE,       struct hailo_allocate_continuous_buffer_params)
+#define HAILO_VDMA_CONTINUOUS_BUFFER_FREE     _IO_(HAILO_VDMA_IOCTL_MAGIC,   HAILO_VDMA_CONTINUOUS_BUFFER_FREE_CODE)
 
 
 enum hailo_non_linux_ioctl_code {

common/hailo_pcie_version.h

@@ -7,7 +7,7 @@
 #define _HAILO_COMMON_PCIE_VERSION_H_
 
 #define HAILO_DRV_VER_MAJOR 4
-#define HAILO_DRV_VER_MINOR 12
-#define HAILO_DRV_VER_REVISION 1
+#define HAILO_DRV_VER_MINOR 13
+#define HAILO_DRV_VER_REVISION 0
 
 #endif /* _HAILO_COMMON_PCIE_VERSION_H_ */

common/pcie_common.c

@@ -87,7 +87,7 @@ static const struct hailo_board_compatibility compat[HAILO_BOARD_TYPE_COUNT] = {
             .max_size = PCIE_HAILO8_FW_CFG_MAX_SIZE,
         },
     },
-    [HAILO_BOARD_TYPE_MERCURY] = {
+    [HAILO_BOARD_TYPE_HAILO15] = {
         .fw_addresses = {
             .boot_fw_header = 0x88000,
             .boot_fw_trigger = 0x88c98,
@@ -99,7 +99,7 @@ static const struct hailo_board_compatibility compat[HAILO_BOARD_TYPE_COUNT] = {
             .atr0_trsl_addr1 = 0x000BE000,
             .raise_ready_offset = 0x1754,
         },
-        .fw_filename = "hailo/mercury_fw.bin",
+        .fw_filename = "hailo/hailo15_fw.bin",
         .board_cfg = {
             .filename = NULL,
             .address = 0,
@@ -116,6 +116,8 @@ static const struct hailo_board_compatibility compat[HAILO_BOARD_TYPE_COUNT] = {
 
 bool hailo_pcie_read_interrupt(struct hailo_pcie_resources *resources, struct hailo_pcie_interrupt_source *source)
 {
+    uint32_t channel_data_source = 0;
+    uint32_t channel_data_dest = 0;
     memset(source, 0, sizeof(*source));
 
     source->interrupt_bitmask = hailo_resource_read32(&resources->config, BCS_ISTATUS_HOST);
@@ -127,13 +129,14 @@ bool hailo_pcie_read_interrupt(struct hailo_pcie_resources *resources, struct ha
     hailo_resource_write32(&resources->config, BCS_ISTATUS_HOST, source->interrupt_bitmask);
 
     if (source->interrupt_bitmask & BCS_ISTATUS_HOST_VDMA_SRC_IRQ_MASK) {
-        source->channel_data_source = hailo_resource_read32(&resources->config, BCS_SOURCE_INTERRUPT_PER_CHANNEL);
-        hailo_resource_write32(&resources->config, BCS_SOURCE_INTERRUPT_PER_CHANNEL, source->channel_data_source);
+        channel_data_source = hailo_resource_read32(&resources->config, BCS_SOURCE_INTERRUPT_PER_CHANNEL);
+        hailo_resource_write32(&resources->config, BCS_SOURCE_INTERRUPT_PER_CHANNEL, channel_data_source);
     }
     if (source->interrupt_bitmask & BCS_ISTATUS_HOST_VDMA_DEST_IRQ_MASK) {
-        source->channel_data_dest = hailo_resource_read32(&resources->config, BCS_DESTINATION_INTERRUPT_PER_CHANNEL);
-        hailo_resource_write32(&resources->config, BCS_DESTINATION_INTERRUPT_PER_CHANNEL, source->channel_data_dest);
+        channel_data_dest = hailo_resource_read32(&resources->config, BCS_DESTINATION_INTERRUPT_PER_CHANNEL);
+        hailo_resource_write32(&resources->config, BCS_DESTINATION_INTERRUPT_PER_CHANNEL, channel_data_dest);
     }
+    source->vdma_channels_bitmap = channel_data_source | channel_data_dest;
 
     return true;
 }
@@ -180,7 +183,7 @@ int hailo_pcie_read_firmware_control(struct hailo_pcie_resources *resources, str
     }
 
     // Copy response buffer
-    hailo_resource_read_buffer(&resources->fw_access, PCIE_REQUEST_SIZE_OFFSET + response_header_size,
+    hailo_resource_read_buffer(&resources->fw_access, PCIE_REQUEST_SIZE_OFFSET + (size_t)response_header_size,
         command->buffer_len, &command->buffer);
 
     return 0;
@@ -231,7 +234,7 @@ static void configure_atr_table(struct hailo_pcie_resources *resources,
 static void write_memory_chunk(struct hailo_pcie_resources *resources,
     hailo_ptr_t dest, u32 dest_offset, const void *src, u32 len)
 {
-    BUG_ON(dest_offset + len > resources->fw_access.size);
+    BUG_ON(dest_offset + len > (u32)resources->fw_access.size);
 
     configure_atr_table(resources, dest);
     (void)hailo_resource_write_buffer(&resources->fw_access, dest_offset, len, src);
@@ -240,7 +243,7 @@ static void write_memory_chunk(struct hailo_pcie_resources *resources,
 static void read_memory_chunk(
     struct hailo_pcie_resources *resources, hailo_ptr_t src, u32 src_offset, void *dest, u32 len)
 {
-    BUG_ON(src_offset + len > resources->fw_access.size);
+    BUG_ON(src_offset + len > (u32)resources->fw_access.size);
 
     configure_atr_table(resources, src);
     (void)hailo_resource_read_buffer(&resources->fw_access, src_offset, len, dest);
@@ -438,17 +441,17 @@ int hailo_pcie_write_config_common(struct hailo_pcie_resources *resources, const
 }
 
 const struct hailo_config_constants* hailo_pcie_get_board_config_constants(const enum hailo_board_type board_type) {
-    BUG_ON(board_type >= HAILO_BOARD_TYPE_COUNT);
+    BUG_ON(board_type >= HAILO_BOARD_TYPE_COUNT || board_type < 0);
     return &compat[board_type].board_cfg;
 }
 
 const struct hailo_config_constants* hailo_pcie_get_user_config_constants(const enum hailo_board_type board_type) {
-    BUG_ON(board_type >= HAILO_BOARD_TYPE_COUNT);
+    BUG_ON(board_type >= HAILO_BOARD_TYPE_COUNT || board_type < 0);
     return &compat[board_type].fw_cfg;
 }
 
 const char* hailo_pcie_get_fw_filename(const enum hailo_board_type board_type) {
-    BUG_ON(board_type >= HAILO_BOARD_TYPE_COUNT);
+    BUG_ON(board_type >= HAILO_BOARD_TYPE_COUNT || board_type < 0);
     return compat[board_type].fw_filename;
 }
 

common/pcie_common.h

@@ -51,7 +51,7 @@
 
 #define PCI_VENDOR_ID_HAILO           0x1e60
 #define PCI_DEVICE_ID_HAILO_HAILO8    0x2864
-#define PCI_DEVICE_ID_HAILO_MERCURY   0x45C4
+#define PCI_DEVICE_ID_HAILO_HAILO15   0x45C4
 
 struct hailo_pcie_resources {
     struct hailo_resource config;               // BAR0
@@ -69,8 +69,7 @@ enum hailo_pcie_interrupt_masks {
 
 struct hailo_pcie_interrupt_source {
     uint32_t interrupt_bitmask;
-    uint32_t channel_data_source;
-    uint32_t channel_data_dest;
+    uint32_t vdma_channels_bitmap;
 };
 
 struct hailo_config_constants {