Update cv.md

Signed-off-by: Ken Keong LEE <hareyakana@hotmail.com>

_pages/cv.md

@@ -23,7 +23,7 @@ Work experience
 Professional skills
 ======
 * experienced using industry EDA tools by Cadence/Synopsys, some layout task, but mainly Spice verification, both digital and analog.
-* JEDEC compliant DRAM circuit design 回路設計, technology node before 1 $\alpha$ based on industry DRAM cadence.
+* JEDEC compliant DRAM circuit design 回路設計, technology node larger than 1 $\alpha$ based on industry DRAM.
 * involved in at least 4~ DRAM projects, including 1 custom DRAM project, refer to Zentel Japan product page. 
 * a good general understanding on the general overview from RTL to GDS workflow, a rough understanding in testing.