Fix DMA FIFO reservation.

hathach · Apr 25, 2024 · 298f7f2 · 298f7f2
1 parent 394dc06
commit 298f7f2
Show file tree

Hide file tree

Showing 3 changed files with 13 additions and 11 deletions.
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -393,9 +393,10 @@ static void bus_reset(uint8_t rhport) {
  // Setup the control endpoint 0
  _allocated_fifo_words_tx = 16;
 
- // DMA needs extra space for processing, needs size confirmation
+ // DMA needs extra space for processing
  if(dma_supported(rhport)) {
- _allocated_fifo_words_tx += 72;
+ uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size;
+ _allocated_fifo_words_tx += reserved;
  }
 
  // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
@@ -805,13 +806,14 @@ void dcd_edpt_close_all(uint8_t rhport) {
  // reset allocated fifo IN
  _allocated_fifo_words_tx = 16;
 
- // DMA needs extra space for processing, needs size confirmation
- if(dma_supported(rhport)) {
- _allocated_fifo_words_tx += 72;
- }
-
  fifo_flush_tx(dwc2, 0x10); // all tx fifo
  fifo_flush_rx(dwc2);
+
+ // DMA needs extra space for processing
+ if(dma_supported(rhport)) {
+ uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size;
+ _allocated_fifo_words_tx += reserved;
+ }
 }
 
 bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) {

diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h
@@ -39,7 +39,7 @@
 
 static const dwc2_controller_t _dwc2_controller[] =
 {
- { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 4096 }
+ { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 16384 }
 };
 
 #define dcache_clean(_addr, _size) data_clean(_addr, _size)

diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h
@@ -214,15 +214,15 @@ union {
  volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep)
 union {
  volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2
- dwc2_ghwcfg2_t  ghwcfg2_bm;
+ volatile dwc2_ghwcfg2_t ghwcfg2_bm;
 };
 union {
  volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3
- dwc2_ghwcfg3_t  ghwcfg3_bm;
+ volatile dwc2_ghwcfg3_t ghwcfg3_bm;
 };
 union {
  volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4
- dwc2_ghwcfg4_t  ghwcfg4_bm;
+ volatile dwc2_ghwcfg4_t ghwcfg4_bm;
 };
  volatile uint32_t glpmcfg; // 054 Core LPM Configuration
  volatile uint32_t gpwrdn; // 058 Power Down