DWC2 DMA support

[HiFiPhile]

Describe the PR
Add Internal DMA support to DWC2.

Status

Model	Core Rev	Enumeration	cdc_ual_ports	audio_4_channel_mic	video_capture_2ch
STM32F407 FS w/wo DMA	2.81a	✔️	✔️	✔️	✔️
STM32F429 FS w/wo DMA	2.81a	✔️	✔️	✔️	✔️
STM32F723 FS + HS w/wo DMA	3.30a	✔️	✔️	✔️	✔️
STM32U5 HS w/wo DMA	4.11a	✔️	✔️	✔️	✔️

Model	Core Rev	Enumeration	cdc_msc_freertos	audio_4_channel_mic_freertos	hid_composite_freertos
ESP32-S3 FS w/wo DMA	4.00a	✔️	✔️	✔️	✔️

Benchmark

STM32F723E-DISCO
IAR 9.50 High-Balanced
I-Cache enabled

Method used in #920, all buffers set to 2048b.

	Throughput	Total CPU Usage
DMA OFF	26.7 MB/s	55%
DMA ON	29.5 MB/s	26%

[HiFiPhile]

dcache code should be removed and add MPU suggestion to make usb ram non cacheable:

• Not all internal buffers are aligned to cache line size and has size of multiple cache line size, speculative read or cache eviction of adjacent variables could lead to racing with DMA.
• Frequent cache clean invalidate hurt performance
• In most cases Cortex-M7 recommend use DTCM where cache is not used

[HiFiPhile]

Don't want to depend on class driver but maybe it's the simplest way.

[HiFiPhile]

Kernel use dwc2->ghwcfg3_bm.total_fifo_size it should be reliable.
We can even remove _dwc2_controller[rhport].ep_fifo_size and use this field instead, except GD32VF103 looks strange.

[leptun]

Just tested the fix in 02ec486 and it solved the issue on my end as well 👍
Also verified the dual-CDC example on a stm32f746-disco board with the HS ULPI phy and that enumerates as well

[roma-jam]

Hi @HiFiPhile ,
May I ask how did you measure the total CPU load?

[hathach]

thank you very much @HiFiPhile again for another great PR. sorry for super late response, I am doing more test with this, seems like it have some issue with my h743 eval which uses external HS PHY. That is ok, I am doing more testing and reading hopefully we could fix and merge this soon.

[HiFiPhile]

seems like it have some issue with my h743 eval which uses external HS PHY

Thanks for testing, it's the combination I'm missing.

May I ask how did you measure the total CPU load?

@roma-jam In short I'm using GPIO toggle in ISR and in event queue processing, then take the averaged sum of 10 cycles.