Authors: Dmitry.Serebryakov@cern.ch, Dmitry.Finogeev@cern.ch
git clone https://github.com/AliceO2Group/alice-fit-fpga.git
git pull --recurse-submodules
source /opt/Xilinx/Vivado/2019.2/settings64.sh
used vivado version:
Vivado v2019.2.1 (64-bit)
SW Build: 2729669 on Thu Dec 5 04:49:17 MST 2019
IP Build: 2729494 on Thu Dec 5 07:38:25 MST 2019
cd alice-fit-fpga/firmware/FT0/PM
vivado -mode batch -source make.tcl
cd alice-fit-fpga/firmware/FT0/TCM
vivado -mode batch -source make.tcl
cd alice-fit-fpga/firmware/FT0/FTM
vivado -mode batch -source make.tcl
Open the TCL console in the Vivado window and type in the following commands:
source ../../tcl/fit.tcl
fit::update_ip_properties
Then git add/commit any new/changed files in the directory ipcore_properties
git add/commit any new/changed VHDL files