verilog: skip compiler directives in enum definition

Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>

Units/parser-verilog.r/systemverilog-github4056.d/expected.tags

@@ -2,3 +2,30 @@ my_enum input.sv /^} my_enum;$/;" T
 OTHER_VAL1 input.sv /^ OTHER_VAL1,$/;" c typedef:my_enum
 OTHER_VAL2 input.sv /^ OTHER_VAL2$/;" c typedef:my_enum
 e input.sv /^my_enum e;$/;" r
+O input.sv /^class O;$/;" C
+complex0_s input.sv /^ } [1:0] complex0_s, complex1_s;$/;" S class:O
+a input.sv /^ logic a,b ;$/;" w struct:O.complex0_s
+b input.sv /^ logic a,b ;$/;" w struct:O.complex0_s
+s0 input.sv /^ logic [15:0] [7:0] s0 , s1;$/;" w struct:O.complex0_s
+s1 input.sv /^ logic [15:0] [7:0] s0 , s1;$/;" w struct:O.complex0_s
+struct0_s input.sv /^ } [15:0] [7:0] struct0_s, struct1_s;$/;" w struct:O.complex0_s
+struct1_s input.sv /^ } [15:0] [7:0] struct0_s, struct1_s;$/;" w struct:O.complex0_s
+enum00_e input.sv /^ enum user_t [1:0] { FOO, BAR, BAZ } [3:0] enum00_e, enum01_e ;$/;" w struct:O.complex0_s
+enum01_e input.sv /^ enum user_t [1:0] { FOO, BAR, BAZ } [3:0] enum00_e, enum01_e ;$/;" w struct:O.complex0_s
+enum10_e input.sv /^ enum logic unsigned{A,B,C}[1:0]enum10_e,enum11_e;$/;" w struct:O.complex0_s
+enum11_e input.sv /^ enum logic unsigned{A,B,C}[1:0]enum10_e,enum11_e;$/;" w struct:O.complex0_s
+d input.sv /^ bit[7:0][1:0]d,e;$/;" w struct:O.complex0_s
+e input.sv /^ bit[7:0][1:0]d,e;$/;" w struct:O.complex0_s
+complex1_s input.sv /^ } [1:0] complex0_s, complex1_s;$/;" S class:O
+a input.sv /^ logic a,b ;$/;" w struct:O.complex1_s
+b input.sv /^ logic a,b ;$/;" w struct:O.complex1_s
+s0 input.sv /^ logic [15:0] [7:0] s0 , s1;$/;" w struct:O.complex1_s
+s1 input.sv /^ logic [15:0] [7:0] s0 , s1;$/;" w struct:O.complex1_s
+struct0_s input.sv /^ } [15:0] [7:0] struct0_s, struct1_s;$/;" w struct:O.complex1_s
+struct1_s input.sv /^ } [15:0] [7:0] struct0_s, struct1_s;$/;" w struct:O.complex1_s
+enum00_e input.sv /^ enum user_t [1:0] { FOO, BAR, BAZ } [3:0] enum00_e, enum01_e ;$/;" w struct:O.complex1_s
+enum01_e input.sv /^ enum user_t [1:0] { FOO, BAR, BAZ } [3:0] enum00_e, enum01_e ;$/;" w struct:O.complex1_s
+enum10_e input.sv /^ enum logic unsigned{A,B,C}[1:0]enum10_e,enum11_e;$/;" w struct:O.complex1_s
+enum11_e input.sv /^ enum logic unsigned{A,B,C}[1:0]enum10_e,enum11_e;$/;" w struct:O.complex1_s
+d input.sv /^ bit[7:0][1:0]d,e;$/;" w struct:O.complex1_s
+e input.sv /^ bit[7:0][1:0]d,e;$/;" w struct:O.complex1_s

Units/parser-verilog.r/systemverilog-github4056.d/input.sv

@@ -8,3 +8,25 @@ typedef enum {
 } my_enum;
 
 my_enum e;
+
+// from Units/parser-verilog.r/systemverilog-struct.d/input.sv
+class O;
+ // complex struct
+ struct packed signed {
+ `include "test1.txt"
+ logic a,b ;
+ logic [15:0] [7:0] s0 , s1;
+ `include "test1.txt"
+ struct {
+ `include "test1.txt"
+ logic x, y; // not emitted
+ `include "test1.txt"
+ } [15:0] [7:0] struct0_s, struct1_s;
+ `include "test1.txt"
+ enum user_t [1:0] { FOO, BAR, BAZ } [3:0] enum00_e, enum01_e ;
+ `include "test1.txt"
+ enum logic unsigned{A,B,C}[1:0]enum10_e,enum11_e;
+ bit[7:0][1:0]d,e;
+ `include "test1.txt"
+ } [1:0] complex0_s, complex1_s;
+endclass

parsers/verilog.c

@@ -1653,6 +1653,9 @@ static int pushMembers (tokenInfo* token, int c)
  {
  verilogKind kind = K_UNDEFINED; // set kind of context for processType()
  bool not_used;
+ c = skipMacro (c, token);
+ if (c == '}')
+ break; // end of struct/union
  if (!isWordToken (c))
  {
  VERBOSE ("Unexpected input: %c\n", c);