AdvanceSynthesis_Using_DesignCompiler

Introduction

Synthesis is process of transferring higher level of abstraction (RTL) to implementable lower level of abstraction . It is the process of transforming RTL to gate-level netlist
Synthesis process can be optimized for speed(timing)/Area/Testability(DFT)/Power
Inputs : RTL,Technology Libraries,Constraints (Environment,clocks,IO Delays etc)
Outputs : Netlist,SDC,Reports etc
Synthesis is described as translation plus logic optimization plus mapping
Translation is performed during Reading the files
Logic optimization and mapping are performed by the compile command

Design Compiler(DC)

From Synopsys are the tool widely used for synthesis
Design Compiler® RTL synthesis solution enables users to meet today's design challenges with concurrent optimization of timing, area, power and test. Design Compiler includes innovative topographical technology that enables a predictable flow resulting in faster time to results. Topographical technology provides timing and area prediction within 10% of the results seen post-layout enabling designers to reduce costly iterations between synthesis and physical implementation. Design Compiler also includes a scalable infrastructure that delivers 2X faster runtime on quad-core platforms.

Benefits

Concurrent optimization of timing, area, power and test
Results correlate within 10% of physical implementation
Removes timing bottlenecks by creating fast critical paths
Gate-to-gate optimization for smaller area on new or legacy designs while maintaining timing Quality of Results (QoR)
Cross-probing between RTL, schematic, and timing reports for fast debug
Offers more flexibility for users to control optimization on specific areas of designs
Enables higher efficiency with integrated static timing analysis, test synthesis and power synthesis
Support for multi voltage and multi supply
2X faster runtime on quad-core compute servers

Synopsys Design Constraints

SDC is a short form of “Synopsys Design Constraint”. SDC is a common format for constraining the design which is supported by almost all Synthesis, PnR and other tools. Generally, timing, power and area constraints of design are provided through the SDC file and this file has extension .sdc.

SDC file syntax is based on TCL format and all commands of sdc file follow the TCL syntax. In sdc file ‘#’ is used to comment a line and ” is used to break the line. SDC file can be generated by the synthesis tool and the same can be used in for PnR.

Goals of Synthesis

To get a Gate Level Netlist
Inserting Clock Gates
Logic Optimization
Inserting DFT Logic
Logic Equivalence between RTL and Netlist should be maintained

Synthesis Flow

Inputs and Outputs of Synthesis

Inputs : RTL,Technology Libraries,Constraints (Environment,clocks,IO Delays etc) and UPF
Outputs : Netlist,SDC,Reports, UPF etc

Design Compiler Environment Setup

$ mkdir DC_WORKSHOP 
$ git clone https://github.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop.git

Loading DC_Shell

Invoking Design Compiler

Lab1_flop_with_en.v

Lab1 db_file optimization

Mapping_optimisation

Delay Information

Area Information

TCL Scipting

Invoking the Design Vision

After Linking the Design with Library files and compiling the design with compile_ultra

Basics of Static Timing Analysis

Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.

Timing Dot Library Exploring Dot Library Files

saed32hvt_tt0p85v25c.lib

Advanced Constraints

Major Design Rule Constraints

Major Design Design Constraints

Loading design get_cells, get_ports, get_nets
get_cells
get_ports
get_nets
get_clocks

Creating Clock Waveform

Clock Network Modelling - Uncertainty, report_timing

Uncertainty: It specifies a window within which a clock edge can occur. In physical design uncertainty will be used to model several factors like jitter (the deviation of clock edge from its ideal position), additional margins and skew (at pre-cts)

There will be different uncertainty values specified for setup and hold As hold check is performed with respect to same clock edge, any deviation in clock edge (jitter) will affect both launch and capture flop in same way. So for hold uncertainty no need to model jitter, this is the reason, why we always see less value for hold uncertainty compared to setup uncertainty. Before CTS, uncertainty will also models the expected skew after implementation of clock tree (post-cts). So, at post-cts stages we will reduce the uncertainty values as actual skew values are available. Setup Uncertainty:

Pre-Cts = Jitter + Skew + Extra setup margin

Cts = Jitter + Extra setup margin

Hold Uncertainty:

Pre-Cts = Skew + Extra hold margin

cts = Extra hold margin