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[GSoC] Updated DC-DC Verilog Generation and Simulations #230

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[GSoC] Updated DC-DC Verilog Generation and Simulations #230

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harshkhandeparkar
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@harshkhandeparkar harshkhandeparkar commented Aug 23, 2023 •
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Related to #211

Changes

  • Updated DC-DC Verilog generation to use the common Python module.
  • Used Mako syntax for the Verilog templates.
  • Fixed and enabled sky130hs platform for the generator (synthesis only).
  • Fixed multiple errors in the custom-defined auxiliary cells' CDL.
  • Simulations
    • Added a netlist extracted from the synthesized Verilog with power pins added.
    • Used the common simulation Python module for running simulations.
    • Added a testbench for the DC-DC simulations using the Mako templating syntax.
    • Currently only runs simulations for the cases in which all configuration pins are high and the case in which all are low.
  • Removed and gitignored unused code or files.

@harshkhandeparkar harshkhandeparkar mentioned this pull request Aug 23, 2023
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@harshkhandeparkar harshkhandeparkar force-pushed the dcdc-verilog-mako branch 2 times, most recently from 34d6d25 to d4f68a1 Compare September 11, 2023 15:48
@msaligane
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@saicharan0112 @chetanyagoyal Have you had a chance to look into this?

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sorry, I just saw this PR. I am not sure if I can check anything from the circuit point of view but the updates made to the scripts are pretty good and are aligning towards some kind of standard. I could add a check for this in my upcoming PR which is to address #245

@msaligane msaligane requested review from andylithia and minghunghw and removed request for alibillalhammoud November 8, 2023 18:39
minghunghw
minghunghw suggested changes Nov 9, 2023
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openfasoc/generators/dcdc-gen/src/DCDC_BUFFER.template.sv Show resolved Hide resolved
openfasoc/generators/dcdc-gen/src/DCDC_NOV_CLKGEN.sv Show resolved Hide resolved
openfasoc/generators/dcdc-gen/flow/Makefile
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What is the reason for removing dependencies for macro placement?

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Neither the macro placement nor the place_six_stage.py file were working. I believe the Python file is incomplete, and the macro placement has some outdated code and no longer works with the latest version of OpenROAD. I had removed them to test if the rest of the flow was working, but it was not. Should I revert these changes?

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@minghungumich ?

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@andylithia can you review this PR.

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Can you revert the changes and submit an issue about the dependency issue you're seeing? I can try to fix it

openfasoc/generators/dcdc-gen/src/DCDC_BUFFER.sv Show resolved Hide resolved
openfasoc/generators/dcdc-gen/src/DCDC_SIX_STAGES_CONV.v Show resolved Hide resolved
openfasoc/generators/dcdc-gen/src/dcdcInst.v Show resolved Hide resolved
openfasoc/generators/dcdc-gen/tools/dcdc_simulation.py Show resolved Hide resolved
andylithia
andylithia reviewed Jan 9, 2024
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Need an additional PR to fix the OpenROAD dependency issue

openfasoc/generators/dcdc-gen/flow/Makefile
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Can you revert the changes and submit an issue about the dependency issue you're seeing? I can try to fix it

@harshkhandeparkar
feat: use the new verilog generation module in dcdc-gen
3b22652 
* imported and used the verilog-generation module in dcdc-gen.py
* updated dcdc_netlist.py to return parameters instead of generating the netlist
@harshkhandeparkar
fix: return stringified powmux_config
6a9b124
@harshkhandeparkar
feat: update dcdc-gen verilog to use Mako syntax
fc8fca9
@harshkhandeparkar
feat: gitignore generated verilog in dcdc-gen
5b89116
@harshkhandeparkar
feat: remove unused code in dcdc_gen.py
8f7b28d
@harshkhandeparkar
feat: added a command to make clean to remove generated verilog in dc…
2c18599 
…dc-gen
@harshkhandeparkar
fix: added missing semicolon in dcdc verilog
721dff6
@harshkhandeparkar
fix: removed simulations from clean command
6318148
@harshkhandeparkar
fix: renamed dcdc-gen module_name to prevent collision
2f87a09
@harshkhandeparkar
fix<dcdc>: run make finish for synth and apr
f9adecc
@harshkhandeparkar
fix<dcdc>: copy the correct files from flow/ to work/
12dde5b
@harshkhandeparkar
feat: uncomment sky130hd_dcdc make command
3bcbc7b
@harshkhandeparkar
feat<dcdc>: added error handling for flow steps
13db917
@harshkhandeparkar
fix<dcdc>: added 2_1_floorplan.def as a prerequisite for the def mani…
af21bea 
…pulation step
@harshkhandeparkar
fix<dcdc>: disabled custom macro placement which was not working
276ca01
@harshkhandeparkar
fix<dcdc>: disabled the noise injection module
de601d5 
* LFSR module used in the noise injection module was missing
@harshkhandeparkar harshkhandeparkar force-pushed the dcdc-verilog-mako branch 2 times, most recently from 915013b to 536e135 Compare January 10, 2024 10:12
@harshkhandeparkar harshkhandeparkar changed the title [GSoC] Updated DC-DC Verilog Generation, Flow, and Simulations [GSoC] Updated DC-DC Verilog Generation and Simulations Jan 12, 2024
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@msaligane msaligane msaligane left review comments

@andylithia andylithia andylithia left review comments

@minghunghw minghunghw minghunghw requested changes

@saicharan0112 saicharan0112 Awaiting requested review from saicharan0112

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@harshkhandeparkar @msaligane @saicharan0112 @andylithia @minghunghw