iLoop32 Architecture

Custom Verilog RISC Architecture

Mini Operating System with iLoop32

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
algoritmos		algoritmos
greybox_tmp		greybox_tmp
modulos		modulos
output_files		output_files
pins		pins
simulation/qsim		simulation/qsim
.gitignore		.gitignore
CPU_Project.qpf		CPU_Project.qpf
CPU_Project.qsf		CPU_Project.qsf
CPU_Project.qws		CPU_Project.qws
CPU_Project_assignment_defaults.qdf		CPU_Project_assignment_defaults.qdf
README.md		README.md
Waveform.vwf		Waveform.vwf
Waveform2.vwf		Waveform2.vwf
Waveform3.vwf		Waveform3.vwf
c5_pin_model_dump.txt		c5_pin_model_dump.txt
cpu.v		cpu.v
cpu.v.bak		cpu.v.bak
hdteste.vwf		hdteste.vwf
loop32i.v		loop32i.v
loop32i.v.bak		loop32i.v.bak
teste.v		teste.v
teste.v.bak		teste.v.bak
teste_cpu_full.vwf		teste_cpu_full.vwf