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In the Flow
Creating stuff that makes and improves computers. 1/0.
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IIT(BHU) Varanasi
- Chennai
- infinite.bio.link
- @infini8_139
- in/lnsaaswath
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riscv-tlv-core
riscv-tlv-core PublicA simple implementation of a RISC-V core (RV32I) written in TL Verilog.
Verilog 2
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riscv-ms-soc
riscv-ms-soc PublicA RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
Verilog 10
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Accelerating_Standard_and_Modified_AES128
Accelerating_Standard_and_Modified_AES128 PublicForked from BalaDhinesh/Accelerating_Standard_and_Modified_AES128
Verilog
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courseraforums
courseraforums PublicForked from elleros/courseraforums
[Implementation Updated] Anonymized versions of the discussion threads from the forums of 60 Coursera MOOCs
Jupyter Notebook
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