Disable LSC L1 caching for ROVs

Disable caching ROV accesses in LSC L1 cache.
intel · Jun 29, 2023 · 07d8a21 · 07d8a21
1 parent 9329aa5
commit 07d8a21
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diff --git a/IGC/Compiler/CISACodeGen/EmitVISAPass.cpp b/IGC/Compiler/CISACodeGen/EmitVISAPass.cpp
@@ -20665,6 +20665,21 @@ LSC_CACHE_OPTS EmitPass::translateLSCCacheControlsFromMetadata(
     Instruction* inst, bool isLoad, bool isTGM) const
 {
     LSC_CACHE_OPTS cacheOpts{ LSC_CACHING_DEFAULT, LSC_CACHING_DEFAULT };
+
+    if (inst &&
+        !m_currShader->m_ModuleMetadata->RasterizerOrderedViews.empty())
+    {
+        const auto& rasterizerOrderedViews = m_currShader->m_ModuleMetadata->RasterizerOrderedViews;
+        if (rasterizerOrderedViews.find(inst->getOperand(0)->getType()->getPointerAddressSpace()) != rasterizerOrderedViews.end())
+        {
+            // Do not cache ROV in non-coherent cache
+            MDNode* node = MDNode::get(
+                inst->getContext(),
+                ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(inst->getContext()), LSC_L1UC_L3C_WB)));
+            inst->setMetadata("lsc.cache.ctrl", node);
+        }
+    }
+
     if (isTGM)
     {
         if (m_pCtx->platform.supportsNonDefaultLSCCacheSetting())

diff --git a/IGC/common/MDFrameWork.h b/IGC/common/MDFrameWork.h
@@ -680,6 +680,7 @@ namespace IGC
         std::map<uint32_t, uint32_t> forceLscCacheList;
         std::vector<SrvMapData> SrvMap;
         std::vector<uint32_t> RasterizerOrderedByteAddressBuffer;
+        std::set<uint32_t> RasterizerOrderedViews;
         unsigned int MinNOSPushConstantSize = 0;
         llvm::MapVector<llvm::GlobalVariable*, int> inlineProgramScopeOffsets;
         ShaderData shaderData;