Fix resolution of 2D block writes with cacheopts

Pick proper operand destination argument index
when resolving 2D block writes with cacheopts.
Add cacheopt 2D block write and read tests.

(cherry picked from commit e50b775)

IGC/Compiler/Optimizer/OpenCLPasses/LSCFuncs/LSCFuncsResolution.cpp

@@ -1064,7 +1064,7 @@ Instruction* LSCFuncsResolution::CreateSubGroup2DBlockOperation(llvm::CallInst&
     Value* imageResHeight = CI.getArgOperand(2);
     Value* imageResPitch = CI.getArgOperand(3);
 
-    SmallVector<Value*, 13> args;
+    SmallVector<Value*, 14> args;
     args.push_back(imageResBaseoffset);
     args.push_back(imageResWidth);
     args.push_back(imageResHeight);
@@ -1114,17 +1114,12 @@ Instruction* LSCFuncsResolution::CreateSubGroup2DBlockOperation(llvm::CallInst&
     }
     else
     {
-        uint32_t blockWriteDstOperandId = 5;
-        if (hasCacheOpts)
-        {
-            blockWriteDstOperandId = 6;
-        }
-        Value *dst = CI.getArgOperand(blockWriteDstOperandId);
-        args.push_back(dst);
+        Value *srcVal = CI.getArgOperand(5);
+        args.push_back(srcVal);
         BlockFunc = GenISAIntrinsic::getDeclaration(
             CI.getCalledFunction()->getParent(),
             GenISAIntrinsic::GenISA_LSC2DBlockWrite,
-            dst->getType());
+            srcVal->getType());
     }
 
     Instruction* BlockOp = CallInst::Create(BlockFunc, args, "", &CI);

IGC/Compiler/tests/LSCFuncsResolution/subgroup_block_read.ll

@@ -55,6 +55,11 @@ define spir_kernel void @test_lsc(i64 %base, <2 x i32> %cord) {
 ; CHECK:    call <32 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v32i16(i64 %base, i32 0, i32 7, i32 0, i32 [[TMP13]], i32 [[TMP14]], i32 16, i32 16, i32 32, i32 2, i1 false, i1 true, i32 0)
   %7 = call <32 x i16> @__builtin_IB_subgroup_block_read_flat_transform_u16_k32v2(i64 %base, i32 0, i32 7, i32 0, <2 x i32> %cord)
 
+; CHECK:    [[TMP15:%.*]] = extractelement <2 x i32> %cord, i32 0
+; CHECK:    [[TMP16:%.*]] = extractelement <2 x i32> %cord, i32 1
+; CHECK:    call <32 x i16> @llvm.genx.GenISA.LSC2DBlockRead.v32i16(i64 %base, i32 0, i32 7, i32 0, i32 [[TMP15]], i32 [[TMP16]], i32 16, i32 16, i32 16, i32 2, i1 false, i1 false, i32 4)
+  %8 = call <32 x i16> @__builtin_IB_subgroup_block_read_flat_cacheopts_u16_m16k16v2(i64 %base, i32 0, i32 7, i32 0, <2 x i32> %cord, i32 4)
+
 ; CHECK:    ret void
   ret void
 }
@@ -69,6 +74,8 @@ declare <16 x i16> @__builtin_IB_subgroup_block_read_flat_transform_u16_k16v2(i6
 declare <16 x i16> @__builtin_IB_subgroup_block_read_flat_transform_u16_k32(i64, i32, i32, i32, <2 x i32>)
 declare <32 x i16> @__builtin_IB_subgroup_block_read_flat_transform_u16_k32v2(i64, i32, i32, i32, <2 x i32>)
 
+declare <32 x i16> @__builtin_IB_subgroup_block_read_flat_cacheopts_u16_m16k16v2(i64, i32, i32, i32, <2 x i32>, i32)
+
 !igc.functions = !{!0}
 
 !0 = !{void (i64, <2 x i32>)* @test_lsc, !1}

IGC/Compiler/tests/LSCFuncsResolution/subgroup_block_write.ll

@@ -0,0 +1,44 @@
+;=========================== begin_copyright_notice ============================
+;
+; Copyright (C) 2024 Intel Corporation
+;
+; SPDX-License-Identifier: MIT
+;
+;============================ end_copyright_notice =============================
+;
+; RUN: igc_opt -enable-debugify --igc-lsc-funcs-translation -platformpvc -S < %s 2>&1 | FileCheck %s
+; ------------------------------------------------
+; LSCFuncsResolution
+; ------------------------------------------------
+
+; Test checks that lsc builtins are lowered
+
+; Debug-info related check
+; CHECK-NOT: WARNING
+; CHECK: CheckModuleDebugify: PASS
+
+define spir_kernel void @test_lsc(i64 %base_dst, <2 x i32> %coord, <8 x i32> %val_to_store) {
+; CHECK-LABEL: @test_lsc(
+
+; CHECK: [[XOFF0:%.*]] = extractelement <2 x i32> %coord, i32 0
+; CHECK: [[YOFF0:%.*]] = extractelement <2 x i32> %coord, i32 1
+; CHECK: call void  @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64 %base_dst, i32 127, i32 7, i32 127, i32 [[XOFF0]], i32 [[YOFF0]], i32 32, i32 16, i32 8, i32 1, i1 false, i1 false, i32 0, <8 x i32> %val_to_store)
+  call void @__builtin_IB_subgroup_block_write_flat_u32_wi8_m8k16v1(i64 %base_dst, i32 127, i32 7, i32 127, <2 x i32> %coord, <8 x i32> %val_to_store)
+
+; CHECK: [[XOFF1:%.*]] = extractelement <2 x i32> %coord, i32 0
+; CHECK: [[YOFF1:%.*]] = extractelement <2 x i32> %coord, i32 1
+; CHECK: call void  @llvm.genx.GenISA.LSC2DBlockWrite.v8i32(i64 %base_dst, i32 127, i32 7, i32 127, i32 [[XOFF1]], i32 [[YOFF1]], i32 32, i32 16, i32 8, i32 1, i1 false, i1 false, i32 2, <8 x i32> %val_to_store)
+  call void @__builtin_IB_subgroup_block_write_flat_cacheopts_u32_wi8_m8k16v1(i64 %base_dst, i32 127, i32 7, i32 127, <2 x i32> %coord, <8 x i32> %val_to_store, i32 2)
+
+; CHECK:    ret void
+  ret void;
+}
+
+declare void @__builtin_IB_subgroup_block_write_flat_u32_wi8_m8k16v1(i64, i32, i32, i32, <2 x i32>, <8 x i32>)
+declare void @__builtin_IB_subgroup_block_write_flat_cacheopts_u32_wi8_m8k16v1(i64, i32, i32, i32, <2 x i32>, <8 x i32>, i32)
+
+!igc.functions = !{!0}
+!0 = !{void (i64, <2 x i32>, <8 x i32>)* @test_lsc, !1}
+!1 = !{!2, !3}
+!2 = !{!"function_type", i32 0}
+!3 = !{!"sub_group_size", i32 16}