[Autobackout][FunctionalRegression]Revert of change: e1259d5: Enable …

…legacy memory intrinsic translation by default .
intel · Aug 7, 2024 · 8e0b6d6 · 8e0b6d6
1 parent 19c6e97
commit 8e0b6d6
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Showing 11 changed files with 18 additions and 28 deletions.
diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td
@@ -383,7 +383,6 @@ def : Proc<"XeHPG", [
  FeatureMultiIndirectByteRegioning,
  FeatureSLM128K,
  FeatureThreadPayloadInMemory,
- FeatureTransLegacy,
 ]>;
 
 def : Proc<"XeLPG", [
@@ -405,7 +404,6 @@ def : Proc<"XeLPG", [
  FeatureMultiIndirectByteRegioning,
  FeatureSLM128K,
  FeatureThreadPayloadInMemory,
- FeatureTransLegacy,
 ]>;
 
 def : Proc<"XeLPGPlus", [
@@ -427,7 +425,6 @@ def : Proc<"XeLPGPlus", [
  FeatureMultiIndirectByteRegioning,
  FeatureSLM128K,
  FeatureThreadPayloadInMemory,
- FeatureTransLegacy,
 ]>;
 
 def : Proc<"XeHPC", [
@@ -454,7 +451,6 @@ def : Proc<"XeHPC", [
  FeatureSLM128K,
  FeatureSwitchjmp,
  FeatureThreadPayloadInMemory,
- FeatureTransLegacy,
 ]>;
 
 def : Proc<"XeHPCVG", [
@@ -481,7 +477,6 @@ def : Proc<"XeHPCVG", [
  FeatureSLM128K,
  FeatureSwitchjmp,
  FeatureThreadPayloadInMemory,
- FeatureTransLegacy,
 ]>;
 
 def : Proc<"Xe2", [

diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXOCLRuntimeInfo.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXOCLRuntimeInfo.cpp
@@ -212,7 +212,7 @@ KernelArgBuilder::getOCLArgKind(ArrayRef<StringRef> Tokens,
  if (any_of(Tokens, getStrPred(OCLAttributes::Image2dArray)))
  return ArgKindType::Image2DArray;
  if (any_of(Tokens, getStrPred(OCLAttributes::Image2dMediaBlock))) {
- if (ST.translateMediaBlockMessages())
+ if (ST.translateLegacyMessages())
  return ArgKindType::Image2D;
  return ArgKindType::Image2DMediaBlock;
  }

diff --git a/IGC/VectorCompiler/test/CisaBuilder/math_f16.ll b/IGC/VectorCompiler/test/CisaBuilder/math_f16.ll
@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023-2024 Intel Corporation
+; Copyright (C) 2023 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -14,7 +14,6 @@
 
 ; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;
 
-; CHECK: .decl {{V[^ ]+}} v_type=G type=hf num_elts=8
 ; CHECK: .decl [[SRC:V[^ ]+]] v_type=G type=hf num_elts=8
 ; CHECK: cos (M1, 8) [[COS:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>
 ; CHECK: exp (M1, 8) [[EXP:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>

diff --git a/IGC/VectorCompiler/test/CisaBuilder/math_f32.ll b/IGC/VectorCompiler/test/CisaBuilder/math_f32.ll
@@ -1,6 +1,6 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023-2024 Intel Corporation
+; Copyright (C) 2023 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
@@ -14,7 +14,6 @@
 
 ; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;
 
-; CHECK: .decl {{V[^ ]+}} v_type=G type=f num_elts=8
 ; CHECK: .decl [[SRC:V[^ ]+]] v_type=G type=f num_elts=8
 ; CHECK: cos (M1, 8) [[COS:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>
 ; CHECK: exp (M1, 8) [[EXP:V[^ ]+]](0,0)<1> [[SRC]](0,0)<1;1,0>

diff --git a/IGC/VectorCompiler/test/CisaBuilder/rdtsc.ll b/IGC/VectorCompiler/test/CisaBuilder/rdtsc.ll
@@ -14,22 +14,19 @@
 
 ; COM: ;;;;;;;;;; CHECKERS ;;;;;;;;;;
 
-; CHECK: .decl [[SURF:V[^ ]+]] v_type=G type=d num_elts=1 align=dword
 ; CHECK: .decl [[TMC_1:V[^ ]+]] v_type=G type=q num_elts=1 align=qword
 ; CHECK: .decl [[TMC_2:V[^ ]+]] v_type=G type=q num_elts=1 align=qword
 ; CHECK: .decl [[RES:V[^ ]+]] v_type=G type=d num_elts=8 align=GRF
-; CHECK: .decl [[ALIAS_SURF:V[^ ]+]] v_type=G type=ud num_elts=1 alias=<[[SURF]], 0>
 ; CHECK: .decl [[ALIAS_1:V[^ ]+]] v_type=G type=d num_elts=2 alias=<[[TMC_1]], 0>
 ; CHECK: .decl [[ALIAS_2:V[^ ]+]] v_type=G type=d num_elts=2 alias=<[[TMC_2]], 0>
 ; CHECK: .decl [[ALIAS_RES:V[^ ]+]] v_type=G type=q num_elts=4 alias=<[[RES]], 0>
 ; CHECK: .decl [[SURFACE:T[^ ]+]] v_type=T num_elts=1
 
-; CHECK: movs (M1, 1) [[ALIAS_SURF]](0,0)<1> [[SURFACE]](0)
 ; CHECK: mov (M1, 2) [[ALIAS_1]](0,0)<1> %tsc(0,0)<1;1,0>
 ; CHECK: mov (M1, 2) [[ALIAS_2]](0,0)<1> %tsc(0,0)<1;1,0>
 ; CHECK: mov (M1, 1) [[ALIAS_RES]](0,0)<1> [[TMC_1]](0,0)<0;1,0>
 ; CHECK: mov (M1, 1) [[ALIAS_RES]](0,1)<1> [[TMC_2]](0,0)<0;1,0>
-; CHECK: lsc_store.ugm (M1, 1) bti([[SURF]])[{{V[^ ]+}}]:a32 [[RES]]:d32x8t
+; CHECK: oword_st (2) [[SURFACE]] 0x0:ud [[RES]]
 
 ; COM: ;;;;;;;;;; KERNEL ;;;;;;;;;;
 

diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/atomic.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/atomic.ll
@@ -1,12 +1,12 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023-2024 Intel Corporation
+; Copyright (C) 2023 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
 ;============================ end_copyright_notice =============================
 
-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s
+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-p:64:64-i64:64-n8:16:32:64"
 target triple = "genx64-unknown-unknown"

diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather-scatter.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather-scatter.ll
@@ -1,13 +1,12 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023-2024 Intel Corporation
+; Copyright (C) 2023 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
 ;============================ end_copyright_notice =============================
 
-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \
-; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s
+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-p:64:64-i64:64-n8:16:32:64"
 target triple = "genx64-unknown-unknown"

diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather4-scatter4.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/gather4-scatter4.ll
@@ -1,13 +1,12 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023-2024 Intel Corporation
+; Copyright (C) 2023 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
 ;============================ end_copyright_notice =============================
 
-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \
-; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s
+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-p:64:64-i64:64-n8:16:32:64"
 target triple = "genx64-unknown-unknown"

diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-ld.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-ld.ll
@@ -10,7 +10,8 @@
 ; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s
 
 ; RUN: %opt %use_old_pass_manager% -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPG \
-; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck --check-prefix=NOTYPED %s
+; RUN: -mattr=+translate_legacy_message -mtriple=spir64-unknown-unknown -S < %s | \
+; RUN: FileCheck --check-prefix=NOTYPED %s
 
 ; COM: media.ld -> llvm.vc.internal.lsc.load.2d.tgm.bti
 

diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-st.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/media-block-st.ll
@@ -7,10 +7,12 @@
 ;============================ end_copyright_notice =============================
 
 ; RUN: %opt %use_old_pass_manager% -GenXLegacyToLscTranslator -march=genx64 -mcpu=Xe2 \
-; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s
+; RUN: -mattr=+translate_legacy_message -mtriple=spir64-unknown-unknown -S < %s | \
+; RUN: FileCheck %s
 
 ; RUN: %opt %use_old_pass_manager% -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPG \
-; RUN: -mtriple=spir64-unknown-unknown -S < %s | FileCheck --check-prefix=NOTYPED %s
+; RUN: -mattr=+translate_legacy_message -mtriple=spir64-unknown-unknown -S < %s | \
+; RUN: FileCheck --check-prefix=NOTYPED %s
 
 ; COM: media.st -> llvm.genx.lsc.store2d.typed.bti
 

diff --git a/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/oword.ll b/IGC/VectorCompiler/test/GenXLegacyToLscTranslator/oword.ll
@@ -1,13 +1,12 @@
 ;=========================== begin_copyright_notice ============================
 ;
-; Copyright (C) 2023-2024 Intel Corporation
+; Copyright (C) 2023 Intel Corporation
 ;
 ; SPDX-License-Identifier: MIT
 ;
 ;============================ end_copyright_notice =============================
 
-; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator \
-; RUN: -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -S < %s 2>&1 | FileCheck %s
+; RUN: %opt %use_old_pass_manager% -enable-debugify -GenXLegacyToLscTranslator -march=genx64 -mcpu=XeHPC -mtriple=spir64-unknown-unknown -mattr=+translate_legacy_message -S < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-p:64:64-i64:64-n8:16:32:64"
 target triple = "genx64-unknown-unknown"