preparing emulation of surfaceIndex values

Begins to plumb dummy surfaceIndex param from parse into vISA (must be 0 until we emulate) visa asm decode changes (no behavior change)
intel · Jun 25, 2023 · 91b6d21 · 91b6d21
1 parent d5cd04a
commit 91b6d21
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Showing 3 changed files with 19 additions and 10 deletions.
diff --git a/visa/CISA.y b/visa/CISA.y
@@ -220,6 +220,7 @@ std::vector<attr_gen_struct*> AttrOptVar;
  } lsc_addr_operand;
  struct {
  VISA_opnd *surface;
+ int surfaceIndex;
  // for UNTYPED
  // simple: regs[0] = reg addr
  // strided: regs[0] = base; regs[1] = strided
@@ -228,7 +229,7 @@ std::vector<attr_gen_struct*> AttrOptVar;
  // for TYPED: {U, V, R, sample index/LOD}
  // for TYPED block2d: regs = {BlockStartX, BlockStartY}
  VISA_opnd *regs[6];
- int immOffsets[2];
+ int  immOffsets[2];
  LSC_ADDR addr;
  } lsc_block2d_addr_operand;
  LSC_ADDR_SIZE lsc_addr_size;
@@ -1907,9 +1908,9 @@ LscTypedReadStateInfo:
 // 4 5 6 7 8
  LscPayloadReg LscRegAddrModel LBRACK LscPayloadReg RBRACK
  {
- LSC_CACHE_OPTS caching{LSC_CACHING_DEFAULT,LSC_CACHING_DEFAULT};
- LSC_DATA_SHAPE dataShape{LSC_DATA_SIZE_32b,LSC_DATA_ORDER_NONTRANSPOSE};
- dataShape.elems = LSC_DATA_ELEMS_1;
+ LSC_CACHE_OPTS caching {LSC_CACHING_DEFAULT,LSC_CACHING_DEFAULT};
+ LSC_DATA_SHAPE dataShape {LSC_DATA_SIZE_32b,LSC_DATA_ORDER_TRANSPOSE};
+ dataShape.elems = LSC_DATA_ELEMS_16;
  pBuilder->CISA_create_lsc_typed_inst(
  $1, // predicate
  $2, // subop
@@ -1992,7 +1993,7 @@ LscUntypedBlock2dAddrOperand:
 // 16
  RBRACK
  {
- $$ = {nullptr,{$3,$5,$7,$9,$11,$14},{(int)$12, (int)$15},{LSC_ADDR_TYPE_FLAT,1,0,LSC_ADDR_SIZE_64b}};
+ $$ = {nullptr,0,{$3,$5,$7,$9,$11,$14},{(int)$12, (int)$15},{LSC_ADDR_TYPE_FLAT,1,0,LSC_ADDR_SIZE_64b}};
  }
  |
 // 1 2
@@ -2012,7 +2013,7 @@ LscUntypedBlock2dAddrOperand:
 // 14
  RBRACK
  {
- $$ = {nullptr,{$3,$5,$7,$9,$11,$13},{0, 0},{LSC_ADDR_TYPE_FLAT,1,0,LSC_ADDR_SIZE_64b}};
+ $$ = {nullptr,0,{$3,$5,$7,$9,$11,$13},{0, 0},{LSC_ADDR_TYPE_FLAT,1,0,LSC_ADDR_SIZE_64b}};
  }
 LscTypedOneAddrOperand:
 // just U

diff --git a/visa/IsaDisassembly.cpp b/visa/IsaDisassembly.cpp
@@ -3120,7 +3120,8 @@ class LscInstFormatter {
  }
  } // formatTyped
 
- // e.g. lsc_read_state_info.tgm VDATA bti(0x4)
+ // e.g. lsc_read_state_info.tgm VDATA bti(0x4)[COORD]
+ // see formatTyped for the parameter order
  void formatTypedRSI() {
  ss << opInfo.mnemonic;
 
@@ -3135,12 +3136,16 @@ class LscInstFormatter {
  (void)getNextEnumU8<LSC_ADDR_SIZE>();
  (void)getNextDataShape();
 
+ int addrSurfIx = currOpIx + 0;
+ int dstIx = currOpIx + 1;
+ int src0Ix = currOpIx + 2;
+
  ss << " ";
- formatRawOperand(currOpIx + 1); // dst
+ formatRawOperand(dstIx); // dst
  ss << " ";
- formatAddrType(addrType, currOpIx); // surface (a0.2)
+ formatAddrType(addrType, addrSurfIx); // surface (a0.2)
  ss << "[";
- formatRawOperand(currOpIx + 2);
+ formatRawOperand(src0Ix);
  ss << "]";
  }
 

diff --git a/visa/VisaToG4/TranslateSendLdStLsc.cpp b/visa/VisaToG4/TranslateSendLdStLsc.cpp
@@ -78,7 +78,10 @@ static MsgOp ConvertLSCOpToMsgOp(LSC_OP op) {
  return MsgOp::ATOMIC_OR;
  case LSC_OP::LSC_FENCE:
  return MsgOp::FENCE;
+ case LSC_OP::LSC_READ_STATE_INFO:
+ return MsgOp::RSI;
  default:
+ vISA_ASSERT_UNREACHABLE("unsupported LSC_OP");
  return MsgOp::INVALID;
  }
 }