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…que pointers support (part 3)

This change is a part of the effort to support opaque pointers in newer
    LLVM versions
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@sys-igc @igcbot
sys-igc authored and igcbot committed Oct 28, 2024
1 parent aa8964c commit ee68bc3
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Showing 48 changed files with 449 additions and 822 deletions.
45 changes: 18 additions & 27 deletions IGC/VectorCompiler/test/LowerAggrCopies/memcpy-const-linear.ll
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@@ -1,49 +1,40 @@
;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2022-2024 Intel Corporation
; Copyright (C) 2022 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================

; RUN: %opt_typed_ptrs %use_old_pass_manager% -genx-lower-aggr-copies -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-TYPED-PTRS
; RUN: %opt_opaque_ptrs %use_old_pass_manager% -genx-lower-aggr-copies -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-OPAQUE-PTRS
; RUN: %opt %use_old_pass_manager% -genx-lower-aggr-copies -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s

target datalayout = "e-p:64:64-i64:64-n8:16:32"

declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1)

define internal spir_func void @foo(i8* %dst, i8* %src) {
; CHECK-TYPED-PTRS: [[src1:%[^ ]+]] = bitcast i8* %src to <1 x i8>*
; CHECK-TYPED-PTRS: [[data1:%[^ ]+]] = load <1 x i8>, <1 x i8>* [[src1]]
; CHECK-TYPED-PTRS: [[dst1:%[^ ]+]] = bitcast i8* %dst to <1 x i8>*
; CHECK-TYPED-PTRS: store <1 x i8> [[data1]], <1 x i8>* [[dst1]]
; CHECK-OPAQUE-PTRS: [[data1:%[^ ]+]] = load <1 x i8>, ptr %src
; CHECK-OPAQUE-PTRS: store <1 x i8> [[data1]], ptr %dst
; CHECK: [[src1:%[^ ]+]] = bitcast i8* %src to <1 x i8>*
; CHECK: [[data1:%[^ ]+]] = load <1 x i8>, <1 x i8>* [[src1]]
; CHECK: [[dst1:%[^ ]+]] = bitcast i8* %dst to <1 x i8>*
; CHECK: store <1 x i8> [[data1]], <1 x i8>* [[dst1]]
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 1, i1 false)

; CHECK-TYPED-PTRS: [[src2:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK-TYPED-PTRS: [[data2:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src2]], align 8
; CHECK-TYPED-PTRS: [[dst2:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK-TYPED-PTRS: store <8 x i8> [[data2]], <8 x i8>* [[dst2]]
; CHECK-OPAQUE-PTRS: [[data2:%[^ ]+]] = load <8 x i8>, ptr %src, align 8
; CHECK-OPAQUE-PTRS: store <8 x i8> [[data2]], ptr %dst
; CHECK: [[src2:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK: [[data2:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src2]], align 8
; CHECK: [[dst2:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK: store <8 x i8> [[data2]], <8 x i8>* [[dst2]]
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* align 8 %src, i64 8, i1 false)

; CHECK-TYPED-PTRS: [[src3:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK-TYPED-PTRS: [[data3:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src3]]
; CHECK-TYPED-PTRS: [[dst3:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK-TYPED-PTRS: store <8 x i8> [[data3]], <8 x i8>* [[dst3]], align 8
; CHECK-OPAQUE-PTRS: [[data3:%[^ ]+]] = load <8 x i8>, ptr %src
; CHECK-OPAQUE-PTRS: store <8 x i8> [[data3]], ptr %dst, align 8
; CHECK: [[src3:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK: [[data3:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src3]]
; CHECK: [[dst3:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK: store <8 x i8> [[data3]], <8 x i8>* [[dst3]], align 8
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %dst, i8* %src, i64 8, i1 false)

; CHECK-TYPED-PTRS: [[src4:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK-TYPED-PTRS: [[data4:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src4]], align 8
; CHECK-TYPED-PTRS: [[dst4:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK-TYPED-PTRS: store <8 x i8> [[data4]], <8 x i8>* [[dst4]], align 8
; CHECK-OPAQUE-PTRS: [[data4:%[^ ]+]] = load <8 x i8>, ptr %src, align 8
; CHECK-OPAQUE-PTRS: store <8 x i8> [[data4]], ptr %dst, align 8
; CHECK: [[src4:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK: [[data4:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src4]], align 8
; CHECK: [[dst4:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK: store <8 x i8> [[data4]], <8 x i8>* [[dst4]], align 8
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %dst, i8* align 8 %src, i64 8, i1 false)

ret void
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45 changes: 18 additions & 27 deletions IGC/VectorCompiler/test/LowerAggrCopies/memmove-const-linear.ll
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Original file line number Diff line number Diff line change
@@ -1,49 +1,40 @@
;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2022-2024 Intel Corporation
; Copyright (C) 2022 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================

; RUN: %opt_typed_ptrs %use_old_pass_manager% -genx-lower-aggr-copies -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-TYPED-PTRS
; RUN: %opt_opaque_ptrs %use_old_pass_manager% -genx-lower-aggr-copies -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-OPAQUE-PTRS
; RUN: %opt %use_old_pass_manager% -genx-lower-aggr-copies -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s

target datalayout = "e-p:64:64-i64:64-n8:16:32"

declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1)

define internal spir_func void @foo(i8* %dst, i8* %src) {
; CHECK-TYPED-PTRS: [[src1:%[^ ]+]] = bitcast i8* %src to <1 x i8>*
; CHECK-TYPED-PTRS: [[data1:%[^ ]+]] = load <1 x i8>, <1 x i8>* [[src1]]
; CHECK-TYPED-PTRS: [[dst1:%[^ ]+]] = bitcast i8* %dst to <1 x i8>*
; CHECK-TYPED-PTRS: store <1 x i8> [[data1]], <1 x i8>* [[dst1]]
; CHECK-OPAQUE-PTRS: [[data1:%[^ ]+]] = load <1 x i8>, ptr %src
; CHECK-OPAQUE-PTRS: store <1 x i8> [[data1]], ptr %dst
; CHECK: [[src1:%[^ ]+]] = bitcast i8* %src to <1 x i8>*
; CHECK: [[data1:%[^ ]+]] = load <1 x i8>, <1 x i8>* [[src1]]
; CHECK: [[dst1:%[^ ]+]] = bitcast i8* %dst to <1 x i8>*
; CHECK: store <1 x i8> [[data1]], <1 x i8>* [[dst1]]
call void @llvm.memmove.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 1, i1 false)

; CHECK-TYPED-PTRS: [[src2:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK-TYPED-PTRS: [[data2:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src2]], align 8
; CHECK-TYPED-PTRS: [[dst2:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK-TYPED-PTRS: store <8 x i8> [[data2]], <8 x i8>* [[dst2]]
; CHECK-OPAQUE-PTRS: [[data2:%[^ ]+]] = load <8 x i8>, ptr %src, align 8
; CHECK-OPAQUE-PTRS: store <8 x i8> [[data2]], ptr %dst
; CHECK: [[src2:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK: [[data2:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src2]], align 8
; CHECK: [[dst2:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK: store <8 x i8> [[data2]], <8 x i8>* [[dst2]]
call void @llvm.memmove.p0i8.p0i8.i64(i8* %dst, i8* align 8 %src, i64 8, i1 false)

; CHECK-TYPED-PTRS: [[src3:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK-TYPED-PTRS: [[data3:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src3]]
; CHECK-TYPED-PTRS: [[dst3:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK-TYPED-PTRS: store <8 x i8> [[data3]], <8 x i8>* [[dst3]], align 8
; CHECK-OPAQUE-PTRS: [[data3:%[^ ]+]] = load <8 x i8>, ptr %src
; CHECK-OPAQUE-PTRS: store <8 x i8> [[data3]], ptr %dst, align 8
; CHECK: [[src3:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK: [[data3:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src3]]
; CHECK: [[dst3:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK: store <8 x i8> [[data3]], <8 x i8>* [[dst3]], align 8
call void @llvm.memmove.p0i8.p0i8.i64(i8* align 8 %dst, i8* %src, i64 8, i1 false)

; CHECK-TYPED-PTRS: [[src4:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK-TYPED-PTRS: [[data4:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src4]], align 8
; CHECK-TYPED-PTRS: [[dst4:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK-TYPED-PTRS: store <8 x i8> [[data4]], <8 x i8>* [[dst4]], align 8
; CHECK-OPAQUE-PTRS: [[data4:%[^ ]+]] = load <8 x i8>, ptr %src, align 8
; CHECK-OPAQUE-PTRS: store <8 x i8> [[data4]], ptr %dst, align 8
; CHECK: [[src4:%[^ ]+]] = bitcast i8* %src to <8 x i8>*
; CHECK: [[data4:%[^ ]+]] = load <8 x i8>, <8 x i8>* [[src4]], align 8
; CHECK: [[dst4:%[^ ]+]] = bitcast i8* %dst to <8 x i8>*
; CHECK: store <8 x i8> [[data4]], <8 x i8>* [[dst4]], align 8
call void @llvm.memmove.p0i8.p0i8.i64(i8* align 8 %dst, i8* align 8 %src, i64 8, i1 false)

ret void
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40 changes: 16 additions & 24 deletions IGC/VectorCompiler/test/LowerAggrCopies/memset_const_linear.ll
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Original file line number Diff line number Diff line change
@@ -1,13 +1,12 @@
;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2020-2024 Intel Corporation
; Copyright (C) 2020-2021 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================

; RUN: %opt_typed_ptrs %use_old_pass_manager% -genx-lower-aggr-copies -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-TYPED-PTRS
; RUN: %opt_opaque_ptrs %use_old_pass_manager% -genx-lower-aggr-copies -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s --check-prefix=CHECK-OPAQUE-PTRS
; RUN: %opt %use_old_pass_manager% -genx-lower-aggr-copies -march=genx64 -mcpu=Gen9 -S < %s | FileCheck %s

target datalayout = "e-p:64:64-i64:64-n8:16:32"

Expand All @@ -16,30 +15,23 @@ declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1 immarg)
define internal spir_func void @foo(i8* %ptr) {
call void @llvm.memset.p0i8.i64(i8* align 2 %ptr, i8 0, i64 16, i1 false)
; COM: align 2 is not enough to use i32
; CHECK-TYPED-PTRS: %[[MS1_PTR:[^ ]+]] = bitcast i8* %ptr to <16 x i8>*
; CHECK-TYPED-PTRS: store <16 x i8> zeroinitializer, <16 x i8>* %[[MS1_PTR]], align 2
; CHECK-OPAQUE-PTRS: store <16 x i8> zeroinitializer, ptr %ptr, align 2
; CHECK: %[[MS1_PTR:[^ ]+]] = bitcast i8* %ptr to <16 x i8>*
; CHECK: store <16 x i8> zeroinitializer, <16 x i8>* %[[MS1_PTR]], align 2

call void @llvm.memset.p0i8.i64(i8* align 4 %ptr, i8 0, i64 20, i1 false)
; CHECK-TYPED-PTRS: %[[MS2_PTR_ALIGN:[^ ]+]] = bitcast i8* %ptr to i32*
; CHECK-TYPED-PTRS: %[[MS2_PTR_BC0:[^ ]+]] = bitcast i32* %[[MS2_PTR_ALIGN]] to <4 x i32>*
; CHECK-TYPED-PTRS: store <4 x i32> zeroinitializer, <4 x i32>* %[[MS2_PTR_BC0]], align 4
; CHECK-TYPED-PTRS: %[[MS2_PTR_OFFSET:[^ ]+]] = getelementptr i32, i32* %[[MS2_PTR_ALIGN]], i32 4
; CHECK-TYPED-PTRS: %[[MS2_PTR_BC1:[^ ]+]] = bitcast i32* %[[MS2_PTR_OFFSET]] to <1 x i32>*
; CHECK-TYPED-PTRS: store <1 x i32> zeroinitializer, <1 x i32>* %[[MS2_PTR_BC1]], align 4
; CHECK-OPAQUE-PTRS: store <4 x i32> zeroinitializer, ptr %ptr, align 4
; CHECK-OPAQUE-PTRS: %[[MS2_PTR_OFFSET:[^ ]+]] = getelementptr i32, ptr %ptr, i32 4
; CHECK-OPAQUE-PTRS: store <1 x i32> zeroinitializer, ptr %[[MS2_PTR_OFFSET]], align 4
; CHECK: %[[MS2_PTR_ALIGN:[^ ]+]] = bitcast i8* %ptr to i32*
; CHECK: %[[MS2_PTR_BC0:[^ ]+]] = bitcast i32* %[[MS2_PTR_ALIGN]] to <4 x i32>*
; CHECK: store <4 x i32> zeroinitializer, <4 x i32>* %[[MS2_PTR_BC0]], align 4
; CHECK: %[[MS2_PTR_OFFSET:[^ ]+]] = getelementptr i32, i32* %[[MS2_PTR_ALIGN]], i32 4
; CHECK: %[[MS2_PTR_BC1:[^ ]+]] = bitcast i32* %[[MS2_PTR_OFFSET]] to <1 x i32>*
; CHECK: store <1 x i32> zeroinitializer, <1 x i32>* %[[MS2_PTR_BC1]], align 4

call void @llvm.memset.p0i8.i64(i8* align 8 %ptr, i8 0, i64 24, i1 false)
; CHECK-TYPED-PTRS: %[[MS3_PTR_ALIGN:[^ ]+]] = bitcast i8* %ptr to i32*
; CHECK-TYPED-PTRS: %[[MS3_PTR_BC0:[^ ]+]] = bitcast i32* %[[MS3_PTR_ALIGN]] to <4 x i32>*
; CHECK-TYPED-PTRS: store <4 x i32> zeroinitializer, <4 x i32>* %[[MS3_PTR_BC0]], align 8
; CHECK-TYPED-PTRS: %[[MS3_PTR_OFFSET:[^ ]+]] = getelementptr i32, i32* %[[MS3_PTR_ALIGN]], i32 4
; CHECK-TYPED-PTRS: %[[MS3_PTR_BC1:[^ ]+]] = bitcast i32* %[[MS3_PTR_OFFSET]] to <2 x i32>*
; CHECK-TYPED-PTRS: store <2 x i32> zeroinitializer, <2 x i32>* %[[MS3_PTR_BC1]], align 4
; CHECK-OPAQUE-PTRS: store <4 x i32> zeroinitializer, ptr %ptr, align 8
; CHECK-OPAQUE-PTRS: %[[MS3_PTR_OFFSET:[^ ]+]] = getelementptr i32, ptr %ptr, i32 4
; CHECK-OPAQUE-PTRS: store <2 x i32> zeroinitializer, ptr %[[MS3_PTR_OFFSET]], align 4
; CHECK: %[[MS3_PTR_ALIGN:[^ ]+]] = bitcast i8* %ptr to i32*
; CHECK: %[[MS3_PTR_BC0:[^ ]+]] = bitcast i32* %[[MS3_PTR_ALIGN]] to <4 x i32>*
; CHECK: store <4 x i32> zeroinitializer, <4 x i32>* %[[MS3_PTR_BC0]], align 8
; CHECK: %[[MS3_PTR_OFFSET:[^ ]+]] = getelementptr i32, i32* %[[MS3_PTR_ALIGN]], i32 4
; CHECK: %[[MS3_PTR_BC1:[^ ]+]] = bitcast i32* %[[MS3_PTR_OFFSET]] to <2 x i32>*
; CHECK: store <2 x i32> zeroinitializer, <2 x i32>* %[[MS3_PTR_BC1]], align 4
ret void
}
12 changes: 5 additions & 7 deletions IGC/VectorCompiler/test/Lowering/stacksave.ll
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Original file line number Diff line number Diff line change
@@ -1,25 +1,23 @@

;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2022-2024 Intel Corporation
; Copyright (C) 2022-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================

; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS
; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS
; RUN: %opt %use_old_pass_manager% -GenXLowering -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s

declare i8* @llvm.stacksave()
declare void @llvm.stackrestore(i8*)

; CHECK-LABEL: @test_stacksave
define spir_func void @test_stacksave() {
; CHECK: [[FESP:%[^ ]+]] = call i64 @llvm.genx.read.predef.reg.i64.i64(i32 10, i64 undef)
; CHECK-TYPED-PTRS: %stack = inttoptr i64 [[FESP]] to i8*
; CHECK-OPAQUE-PTRS: %stack = inttoptr i64 [[FESP]] to ptr
; CHECK: %stack = inttoptr i64 [[FESP]] to i8*
%stack = call i8* @llvm.stacksave()
; CHECK-TYPED-PTRS: [[PTI:%[^ ]+]] = ptrtoint i8* %stack to i64
; CHECK-OPAQUE-PTRS: [[PTI:%[^ ]+]] = ptrtoint ptr %stack to i64
; CHECK: [[PTI:%[^ ]+]] = ptrtoint i8* %stack to i64
; CHECK: call i64 @llvm.genx.write.predef.reg.i64.i64(i32 10, i64 [[PTI]])
call void @llvm.stackrestore(i8* %stack)
ret void
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14 changes: 5 additions & 9 deletions IGC/VectorCompiler/test/PatternMatch/WrRegion_optimize.ll
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Original file line number Diff line number Diff line change
@@ -1,13 +1,12 @@
;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2021-2024 Intel Corporation
; Copyright (C) 2021-2023 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================

; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXPatternMatch -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS
; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXPatternMatch -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS
; RUN: %opt %use_old_pass_manager% -GenXPatternMatch -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s

declare <16 x i32> @llvm.genx.rdregioni.v16i32.v64i32.i16(<64 x i32>, i32, i32, i32, i16, i32)
declare <16 x i32> @llvm.genx.wrregioni.v16i32.v16i32.i16.v16i1(<16 x i32>, <16 x i32>, i32, i32, i32, i16, i32, <16 x i1>)
Expand All @@ -26,12 +25,9 @@ declare <16 x i8 addrspace(1)*> @llvm.genx.wrregioni.v16p1i8.i16.i1(<16 x i8 add

; CHECK-LABEL: @test_ptr_vector
define <16 x i8 addrspace(1)*> @test_ptr_vector(i8 addrspace(1)* %p) {
; CHECK-TYPED-PTRS: [[CAST:%[^ ]+]] = bitcast i8 addrspace(1)* %p to <1 x i8 addrspace(1)*>
; CHECK-TYPED-PTRS: [[SPLAT:%[^ ]+]] = call <16 x i8 addrspace(1)*> @llvm.genx.rdregioni.v16p1i8.v1p1i8.i16(<1 x i8 addrspace(1)*> [[CAST]], i32 0, i32 16, i32 0, i16 0, i32 undef)
; CHECK-TYPED-PTRS: ret <16 x i8 addrspace(1)*> [[SPLAT]]
; CHECK: [[CAST:%[^ ]+]] = bitcast i8 addrspace(1)* %p to <1 x i8 addrspace(1)*>
; CHECK: [[SPLAT:%[^ ]+]] = call <16 x i8 addrspace(1)*> @llvm.genx.rdregioni.v16p1i8.v1p1i8.i16(<1 x i8 addrspace(1)*> [[CAST]], i32 0, i32 16, i32 0, i16 0, i32 undef)
; CHECK: ret <16 x i8 addrspace(1)*> [[SPLAT]]
%broadcast = call <16 x i8 addrspace(1)*> @llvm.genx.wrregioni.v16p1i8.i16.i1(<16 x i8 addrspace(1)*> undef, i8 addrspace(1)* %p, i32 0, i32 1, i32 0, i16 0, i32 undef, i1 true)
; CHECK-OPAQUE-PTRS: [[CAST:%[^ ]+]] = bitcast ptr addrspace(1) %p to <1 x ptr addrspace(1)>
; CHECK-OPAQUE-PTRS: [[SPLAT:%[^ ]+]] = call <16 x ptr addrspace(1)> @llvm.genx.rdregioni.v16p1.v1p1.i16(<1 x ptr addrspace(1)> [[CAST]], i32 0, i32 16, i32 0, i16 0, i32 undef)
; CHECK-OPAQUE-PTRS: ret <16 x ptr addrspace(1)> [[SPLAT]]
ret <16 x i8 addrspace(1)*> %broadcast
}
8 changes: 3 additions & 5 deletions IGC/VectorCompiler/test/PatternMatch/load_same_constants.ll
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Original file line number Diff line number Diff line change
@@ -1,13 +1,12 @@
;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2020-2024 Intel Corporation
; Copyright (C) 2020-2021 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================

; RUN: %opt_typed_ptrs %use_old_pass_manager% -GenXPatternMatch -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-TYPED-PTRS
; RUN: %opt_opaque_ptrs %use_old_pass_manager% -GenXPatternMatch -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-OPAQUE-PTRS
; RUN: %opt %use_old_pass_manager% -GenXPatternMatch -march=genx64 -mcpu=Gen9 -mtriple=spir64-unknown-unknown -S < %s | FileCheck %s

define dllexport spir_kernel void @test(<16 x i32>* %val, i1 %cond) {
; CHECK: [[CONSTANT:%.*]] = call <1 x i32> @llvm.genx.constanti.v1i32(<1 x i32> <i32 1>)
Expand All @@ -22,8 +21,7 @@ bb2:

bb3:
; CHECK: bb3:
; CHECK-TYPED-PTRS-NEXT: store <16 x i32> [[CONSTANT_SPLAT]], <16 x i32>* %val
; CHECK-OPAQUE-PTRS-NEXT: store <16 x i32> [[CONSTANT_SPLAT]], ptr %val
; CHECK-NEXT: store <16 x i32> [[CONSTANT_SPLAT]], <16 x i32>* %val
%.sink101 = phi <16 x i32> [ <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %bb1 ], [ <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %bb2 ]
store <16 x i32> %.sink101, <16 x i32>* %val
ret void
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