Increase cache size #2264
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Increase cache size #2264
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Signed-off-by: Anatoly Myachev <anatoly.myachev@intel.com>
anmyachev
commented
Sep 17, 2024
| # before each kernel call to make sure that the L2 cache | ||
| # doesn't contain any input data before the run | ||
| cache_size = 256 * 1024 * 1024 | ||
| cache_size = 512 * 1024 * 1024 |
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This increases the difference from the upstream, so it will be necessary to come up with a mechanism in Triton itself to parameterize this value.
Note: we can't make this change only in benchmark_testing.py because testing.py file is used for benchmarking upstream PyTorch.
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PyTorch passes device properties. Wondering if we can use info::device::global_mem_cache_size to determine the size of the cache here somehow
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Checking the impact
CI: https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/10890455942
CI: https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/10891992012 (without IPEX)
AFAIK clearing 256MB L2 cache isn't enough for our main benchmarking system. The performance numbers get a little worse when increasing this way, however it seems we should do it (not necessary, since we only use one tile).