[SYCL][COMPAT][Docs] Updated nd_barrier readme info

sycl/doc/syclcompat/README.md

@@ -1129,17 +1129,24 @@ spec, and so should be used with caution.
 namespace syclcompat {
 namespace experimental {
 
+ #if defined(__AMDGPU__) || defined(__NVPTX__)
+// seq_cst currently not working with AMD and Nvidia Backends
+constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::acq_rel;
+#else
+constexpr sycl::memory_order barrier_memory_order = sycl::memory_order::seq_cst;
+#endif
+
 template <int dimensions = 3>
 inline void nd_range_barrier(
  sycl::nd_item<dimensions> item,
- sycl::atomic_ref<unsigned int, sycl::memory_order::acq_rel,
+ sycl::atomic_ref<unsigned int, barrier_memory_order,
  sycl::memory_scope::device,
  sycl::access::address_space::global_space> &counter);
 
 template <>
 inline void nd_range_barrier(
  sycl::nd_item<1> item,
- sycl::atomic_ref<unsigned int, sycl::memory_order::acq_rel,
+ sycl::atomic_ref<unsigned int, barrier_memory_order,
  sycl::memory_scope::device,
  sycl::access::address_space::global_space> &counter);