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Address PR comments
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fineg74 committed Feb 8, 2024
1 parent 4bb7456 commit b97483c
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Showing 6 changed files with 25 additions and 10 deletions.
2 changes: 1 addition & 1 deletion llvm/lib/SYCLLowerIR/ESIMD/LowerESIMD.cpp
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Expand Up @@ -1011,9 +1011,9 @@ static void translateScatterStore(CallInst &CI, bool IsSLM) {
ESIMDIntrinDesc::GenXArgConversion::TO_I64);
Align AlignValue(Val.getZExtValue());

auto ValsOp = CI.getArgOperand(0);
auto OffsetsOp = CI.getArgOperand(1);
auto MaskOp = CI.getArgOperand(2);
auto ValsOp = CI.getArgOperand(0);
auto DataType = ValsOp->getType();

// Convert the mask from <N x i16> to <N x i1>.
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4 changes: 2 additions & 2 deletions sycl/test-e2e/ESIMD/unified_memory_api/scatter_usm.cpp
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Expand Up @@ -10,8 +10,8 @@

// The test verifies esimd::scatter() functions accepting USM pointer
// and optional compile-time esimd::properties.
// The scatter() calls in this test do not use cache-hint
// properties to not impose using DG2/PVC features.
// The scatter() calls in this test do not use cache-hint properties
// or VS > 1 (number of stores per offset) to not impose using PVC features.

#include "Inputs/scatter.hpp"

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Expand Up @@ -12,7 +12,7 @@
// The test verifies esimd::scatter() functions accepting USM pointer
// and optional compile-time esimd::properties.
// The scatter() calls in this test do not use cache-hint properties
// or VS > 1 (number of loads per offset) to not impose using PVC features.
// or VS > 1 (number of stores per offset) to not impose using PVC features.
//
// TODO: Remove this test when GPU driver issue with llvm.masked.scatter is
// resolved and ESIMD starts using llvm.masked.scatter by default.
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6 changes: 3 additions & 3 deletions sycl/test-e2e/ESIMD/unified_memory_api/slm_scatter.cpp
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Expand Up @@ -8,9 +8,9 @@
// RUN: %{build} -fsycl-device-code-split=per_kernel -D__ESIMD_GATHER_SCATTER_LLVM_IR -o %t.out
// RUN: %{run} %t.out

// The test verifies esimd::slm_scatter() functions accepting
// optional compile-time esimd::properties.
// The scatter() calls in this test do not use DG2/PVC features.
// The test verifies esimd::slm_scatter() functions accepting optional
// compile-time esimd::properties. The slm_scatter() calls in this test do not
// use VS > 1 (number of stores per offset) to not impose using PVC features.

#include "Inputs/scatter.hpp"

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6 changes: 3 additions & 3 deletions sycl/test-e2e/ESIMD/unified_memory_api/slm_scatter_legacy.cpp
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Expand Up @@ -9,9 +9,9 @@
// RUN: %{build} -fsycl-device-code-split=per_kernel -o %t.out
// RUN: %{run} %t.out

// The test verifies esimd::scatter() functions accepting optional compile-time
// esimd::properties. The scatter() calls in this test do not use VS > 1 (number
// of loads per offset) to not impose using PVC features.
// The test verifies esimd::slm_scatter() functions accepting optional
// compile-time esimd::properties. The slm_scatter() calls in this test do not
// use VS > 1 (number of stores per offset) to not impose using PVC features.
//
// TODO: Remove this test when GPU driver issue with llvm.masked.scatter is
// resolved and ESIMD starts using llvm.masked.scatter by default.
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15 changes: 15 additions & 0 deletions sycl/test/esimd/memory_properties.cpp
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Expand Up @@ -1281,6 +1281,14 @@ test_gather_scatter(AccType &acc, LocalAccType &local_acc, float *ptrf,
scatter<float, 32, 2>(ptrf, ioffset_n16_view, usm_view, mask_n16);

scatter<float, 32, 2>(ptrf, ioffset_n16_view, usm_view);

simd<uint32_t, 10> ioffset_n10(byte_offset32, 8);
simd<float, 10> usm_n10;

// Check special case to verify that for cases when N is not power of 2 llvm
// intrinsic is used
// CHECK-COUNT-1: call void @llvm.masked.scatter.v10f32.v10p4(<10 x float> {{[^)]+}}, <10 x ptr addrspace(4)> {{[^)]+}}, i32 4, <10 x i1> {{[^)]+}})
scatter(ptrf, ioffset_n10, usm_n10);
}

// CHECK-LABEL: define {{.*}} @_Z23test_slm_gather_scatter{{.*}}
Expand Down Expand Up @@ -1429,4 +1437,11 @@ test_slm_gather_scatter(int byte_offset32) {
slm_scatter<float, 32, 2>(ioffset_n16_view, slm, mask_n16, props_align4);
slm_scatter<float, 32, 2>(ioffset_n16, slm_view, mask_n16, props_align4);
slm_scatter<float, 32, 2>(ioffset_n16_view, slm_view, mask_n16, props_align4);

simd<uint32_t, 10> ioffset_n10(byte_offset32, 8);
simd<float, 10> usm_n10;
// Check special case to verify that for cases when N is not power of 2 llvm
// intrinsic is used
// CHECK-COUNT-1: call void @llvm.masked.scatter.v10f32.v10p3(<10 x float> {{[^)]+}}, <10 x ptr addrspace(3)> {{[^)]+}}, i32 4, <10 x i1> {{[^)]+}})
slm_scatter(ioffset_n10, usm_n10);
}

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