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[SYCL][FPGA] Fix the way we handle duplicate vs conflicting values wi…
…th loop attributes (#14342) This patch improves diagnostic supports by resolving bugs the way we handle duplicate vs conflicting values with the following SYCL FPGA loop attributes: [[intel::max_reinvocation_delay()]] [[intel::initiation_interval()]] [[intel::max_concurrency()]] [[intel::speculated_iterations()]] [[intel::max_interleaving()]] The patch addresses issues in the test case below, which previously missed diagnostics due to a discontinuation in the while loop while checking for duplicate versus conflicting attribute values in the routine CheckForDuplicateAttrs(). Example with `speculated_iterations' attribute: Before the fix: [[intel::speculated_iterations(1)]] // expected-note {{previous attribute is here}} [[intel::speculated_iterations(1)]] // OK [[intel::speculated_iterations(2)]] // expected-error {{conflicting loop attribute 'speculated_iterations'}} [[intel::speculated_iterations(4)]] // OK for (int i = 0; i != 10; ++i) { a[i] = 0; } After the fix: [[intel::speculated_iterations(1)]] // expected-note 2 {{previous attribute is here}} [[intel::speculated_iterations(1)]] // OK [[intel::speculated_iterations(2)]] // expected-error {{conflicting loop attribute 'speculated_iterations'}} [[intel::speculated_iterations(4)]] // expected-error {{conflicting loop attribute 'speculated_iterations'}} for (int i = 0; i != 10; ++i) { a[i] = 0; } Signed-off-by: Soumi Manna <soumi.manna@intel.com> --------- Signed-off-by: Soumi Manna <soumi.manna@intel.com>
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