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[SYCL][FPGA] Rename [[intel::disable_loop_pipelining]] attribute function metadata #11372

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merged 6 commits into from
Oct 12, 2023
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[SYCL][FPGA] Rename [[intel::disable_loop_pipelining]] attribute function metadata #11372

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d14353e
[SYCL][FPGA] Rename [[intel::disable_loop_pipelining]] attribute meta…
smanna12 Oct 2, 2023
d27d105
Fix clang format errors
smanna12 Oct 2, 2023
eab3428
Revert loop metadata changs, update function metadata, and rename file
smanna12 Oct 6, 2023
47241ba
revert loop codegen change
smanna12 Oct 6, 2023
4226e86
Fix clang format errors
smanna12 Oct 6, 2023
624a580
Update doc with small suggested nit
smanna12 Oct 12, 2023
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9 changes: 4 additions & 5 deletions clang/include/clang/Basic/AttrDocs.td
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Expand Up @@ -3357,11 +3357,10 @@ def SYCLIntelDisableLoopPipeliningAttrDocs : Documentation {
let Heading = "intel::disable_loop_pipelining";
let Content = [{
This attribute applies to a loop or a function. Takes no arguments and
disables pipelining of the loop or function data path, causing the loop
or function to be executed serially. Cannot be used on the same loop or
function, or in conjunction with ``speculated_iterations``, ``max_concurrency``,
``initiation_interval``, ``ivdep``, ``max_reinvocation_delay`` or
``enable_loop_pipelining`` attribute.
indicates that the kernel should be pipelined or not. Cannot be used on the
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same loop or function, or in conjunction with ``speculated_iterations``,
``max_concurrency``, ``initiation_interval``, ``ivdep``,
``max_reinvocation_delay`` or ``enable_loop_pipelining`` attribute.
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Thanks @bowenxue-intel for reviews. We added support for "enable_loop_pipeling" on #9263

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Hi @smanna12 , after talking it over with some of my colleagues, we decided with the knowledge that both [[intel::disable_loop_pipelining]] and [[intel::enable_loop_pipelining]] are currently generating the same metadata, to leave the implementation for that as is in order to be unified in the SPIR-V translation side.

I believe you can revert your changes in this file, CGLoopInfo.cpp, and intel-fpga-loops.cpp

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Thanks @bowenxue-intel for the update.

I believe you can revert your changes in this file, CGLoopInfo.cpp, and intel-fpga-loops.cpp

Sure. Done


.. code-block:: c++

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11 changes: 6 additions & 5 deletions clang/lib/CodeGen/CGLoopInfo.cpp
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Expand Up @@ -575,11 +575,12 @@ MDNode *LoopInfo::createMetadata(
}

// disable_loop_pipelining attribute corresponds to
// 'llvm.loop.intel.pipelining.enable, i32 0' metadata
// 'llvm.loop.intel.pipelining.disable, i32 1' metadata
if (Attrs.SYCLLoopPipeliningDisable) {
Metadata *Vals[] = {MDString::get(Ctx, "llvm.loop.intel.pipelining.enable"),
ConstantAsMetadata::get(
ConstantInt::get(llvm::Type::getInt32Ty(Ctx), 0))};
Metadata *Vals[] = {
MDString::get(Ctx, "llvm.loop.intel.pipelining.disable"),
ConstantAsMetadata::get(
ConstantInt::get(llvm::Type::getInt32Ty(Ctx), 1))};
LoopProperties.push_back(MDNode::get(Ctx, Vals));
}

Expand Down Expand Up @@ -1026,7 +1027,7 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx,
// without parameter - 'lvm.loop.coalesce.enable' metadata will be emitted
// n - 'llvm.loop.coalesce.count, i32 n' metadata will be emitted
// For attribute disable_loop_pipelining:
// 'llvm.loop.intel.pipelining.enable, i32 0' metadata will be emitted
// 'llvm.loop.intel.pipelining.disable, i32 1' metadata will be emitted
// For attribute max_interleaving:
// n - 'llvm.loop.max_interleaving.count, i32 n' metadata will be emitted
// For attribute speculated_iterations:
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2 changes: 1 addition & 1 deletion clang/lib/CodeGen/CodeGenFunction.cpp
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Expand Up @@ -790,7 +790,7 @@ void CodeGenFunction::EmitKernelMetadata(const FunctionDecl *FD,
if (FD->hasAttr<SYCLIntelDisableLoopPipeliningAttr>()) {
llvm::Metadata *AttrMDArgs[] = {
llvm::ConstantAsMetadata::get(Builder.getInt32(1))};
Fn->setMetadata("disable_loop_pipelining",
Fn->setMetadata("disable_kernel_pipelining",
llvm::MDNode::get(Context, AttrMDArgs));
}

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4 changes: 2 additions & 2 deletions clang/test/CodeGenSYCL/disable_loop_pipelining.cpp
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Expand Up @@ -29,8 +29,8 @@ int main() {
return 0;
}

// CHECK: define dso_local spir_kernel void @{{.*}}test_kernel1() #0 {{.*}} !disable_loop_pipelining ![[NUM5:[0-9]+]]
// CHECK: define dso_local spir_kernel void @{{.*}}test_kernel1() #0 {{.*}} !disable_kernel_pipelining ![[NUM5:[0-9]+]]
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// CHECK: define dso_local spir_kernel void @{{.*}}test_kernel2() #0 {{.*}} ![[NUM4:[0-9]+]]
// CHECK: define dso_local spir_kernel void @{{.*}}test_kernel3() #0 {{.*}} !disable_loop_pipelining ![[NUM5]]
// CHECK: define dso_local spir_kernel void @{{.*}}test_kernel3() #0 {{.*}} !disable_kernel_pipelining ![[NUM5]]
// CHECK: ![[NUM4]] = !{}
// CHECK: ![[NUM5]] = !{i32 1}
2 changes: 1 addition & 1 deletion clang/test/CodeGenSYCL/intel-fpga-loops.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ void disable_loop_pipelining() {
int a[10];
// CHECK: ![[MD_DLP]] = distinct !{![[MD_DLP]], ![[MP:[0-9]+]], ![[MD_dlp:[0-9]+]]}
// CHECK-NEXT: ![[MP]] = !{!"llvm.loop.mustprogress"}
// CHECK-NEXT: ![[MD_dlp]] = !{!"llvm.loop.intel.pipelining.enable", i32 0}
// CHECK-NEXT: ![[MD_dlp]] = !{!"llvm.loop.intel.pipelining.disable", i32 1}
[[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i)
a[i] = 0;
}
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