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sycl-rel_5_2_0: [UR] CI for UR PR refactor-guess-local-worksize (#12663) #13407

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@kbenzie kbenzie commented Apr 15, 2024

Cherry-pick for sycl-rel_5_2_0 depends on #13405

oneapi-src/unified-runtime#1326


Co-authored-by: Kenneth Benzie (Benie) k.benzie@codeplay.com

nrspruit and others added 5 commits April 15, 2024 05:37
intel#12983)

… info

pre-commit PR for
oneapi-src/unified-runtime#1429

---------

Signed-off-by: Neil R. Spruit <neil.r.spruit@intel.com>
Co-authored-by: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
Implement `seq_cst` RC11/ptx6.0 memory consistency for CUDA backend.

See https://dl.acm.org/doi/pdf/10.1145/3297858.3304043 and
https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#memory-consistency-model
for full details. Requires sm_70 or above. With this PR there is now a
complete mapping between SYCL memory consistency model capabilities and
the official CUDA model, fully exploiting CUDA capabilities when
possible on supported arches.

This makes the SYCL-CTS atomic_ref tests fully pass for sm_70 on the
cuda backend.

Fixes intel#11208

Depends on intel#12907

---------

Signed-off-by: JackAKirk <jack.kirk@codeplay.com>
Co-authored-by: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
oneapi-src/unified-runtime#1326

---------

Co-authored-by: Kenneth Benzie (Benie) <k.benzie@codeplay.com>
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6 participants